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IDT72255LA Datasheet

  • IDT72255LA

  • CMOS SUPERSYNC FIFO?

  • 354.38KB

  • IDT

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CMOS SUPERSYNC FIFO鈩?/div>
8,192 x 18
16,384 x 18
Integrated Device Technology, Inc.
IDT72255LA
IDT72265LA
FEATURES:
鈥?Choose among the following memory organizations:
IDT72255LA
8,192 x 18
IDT72265LA
16,384 x 18
鈥?Pin-compatible with the IDT72275/72285 SuperSync FIFOs
鈥?10ns read/write cycle time (8ns access time)
鈥?Fixed, low first word data latency time
鈥?Auto power down minimizes standby power consumption
鈥?Master Reset clears entire FIFO
鈥?Partial Reset clears data, but retains programmable
settings
鈥?Retransmit operation with fixed, low first word data
latency time
鈥?Empty, Full and Half-Full flags signal FIFO status
鈥?Programmable Almost-Empty and Almost-Full flags, each
flag can default to one of two preselected offsets
鈥?Program partial flags by either serial or parallel means
鈥?Select IDT Standard timing (using
EF
and
FF
flags) or First
Word Fall Through timing (using
OR
and
IR
flags)
鈥?Output enable puts data outputs into high impedance state
鈥?Easily expandable in depth and width
鈥?Independent Read and Write clocks (permit reading and
writing simultaneously)
鈥?Available in the 64-pin Thin Quad Flat Pack (TQFP) and the
64-pin Slim Thin Quad Flat Pack (STQFP)
鈥?High-performance submicron CMOS technology
鈥?Industrial temperature range (鈥?0擄C to +85擄C) is available
DESCRIPTION:
The IDT72255LA/72265LA are exceptionally deep, high
speed, CMOS First-In-First-Out (FIFO) memories with clocked
read and write controls. These FIFOs offer numerous improve-
ments over previous SuperSync FIFOs, including the following:
鈥?The limitation of the frequency of one clock input with
respect to the other has been removed. The Frequency
Select pin (FS) has been removed, thus it is no longer
necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
鈥?The period required by the retransmit operation is now fixed
and short.
FUNCTIONAL BLOCK DIAGRAM
WCLK
D
0
-D
17
INPUT REGISTER
OFFSET REGISTER
/
WRITE CONTROL
LOGIC
RAM ARRAY
8,192 x 18
16,384 x 18
FLAG
LOGIC
/
FWFT/SI
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
OUTPUT REGISTER
RESET
LOGIC
RCLK
Q
0
-Q
17
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
4670 drw 01
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
漏2001 Integrated Device Technology, Inc
APRIL 2001
DSC-4670/1
1

IDT72255LA PDF文件相關(guān)型號(hào)

IDT72255LA,IDT72255LA10PF,IDT72255LA10PFI,IDT72255LA10TF,IDT72255LA10TFI,IDT72255LA15PF,IDT72255LA15PFI,IDT72255LA15TF,IDT72255LA15TFI,IDT72255LA20PF,IDT72255LA20PFI,IDT72255LA20TF,IDT72255LA20TFI,IDT72265LA,IDT72265LA10PF,IDT72265LA10PFI,IDT72265LA10TF,IDT72265LA10TFI,IDT72265LA15PF,IDT72265LA15PFI,IDT72265LA15TF,IDT72265LA15TFI,IDT72265LA20PF,IDT72265LA20PFI,IDT72265LA20TF,IDT72265LA20TFI

IDT72255LA相關(guān)型號(hào)PDF文件下載

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