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IDT7223611L30PQF Datasheet

  • IDT7223611L30PQF

  • CMOS SyncFIFO 64 x 36

  • 20頁

  • IDT

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CMOS SyncFIFO
64 x 36
Integrated Device Technology, Inc.
IDT723611
FEATURES:
鈥?Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
鈥?64 x 36 storage capacity
鈥?Synchronous data buffering from Port A to Port B
鈥?Mailbox bypass register in each direction
鈥?Programmable Almost-Full (
AF
) and Almost-Empty (
AE
)
flags
鈥?Microprocessor Interface Control Logic
鈥?Full Flag (
FF
) and Almost-Full (
AF
) flags synchronized by
CLKA
鈥?Empty Flag (
EF
) and Almost-Empty (
AE
) flags synchro-
nized by CLKB
鈥?Passive parity checking on each Port
鈥?Parity Generation can be selected for each Port
鈥?Supports clock frequencies up to 67MHz
鈥?Fast access times of 10ns
鈥?Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
鈥?Low-power advanced CMOS technology
鈥?Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military elecrical specifications
DESCRIPTION:
The IDT723611 is a monolithic, high-speed, low-power,
CMOS Synchronous (clocked) FIFO memory which supports
clock frequencies up to 67MHz and has read access times as
fast as 10ns. The 64 x 36 dual-port FIFO buffers data from Port
A to Port B. The FIFO has flags to indicate empty and full
conditions, and two programmable flags, Almost-Full (
AF
) and
Almost-Empty (
AE
), to indicate when a selected number of
words is stored in memory. Communication between each
port can take place through two 36-bit mailbox registers. Each
FUNCTIONAL BLOCK DIAGRAM
CLKA
W/
R
A
ENA
MBA
CSA
Port-A
Control
Logic
Parity
Gen/Check
Parity
Generation
MBF1
PEFB
PGB
RST
ODD/
Mail 1
Register
Input
Register
Reset
Logic
EVEN
36
64 x 36
SRAM
Output
Register
鈥?/div>
36
A
0
- A
35
Write
Pointer
Read
Pointer
B
0
- B
35
FF
AF
FIFO
Status Flag
Logic
Programmable
Flag Offset
Registers
EF
AE
FS
0
FS
1
PGA
PEFA
MBF2
Parity
Gen/Check
Mail 2
Register
CLKB
Port-B
Control
Logic
ENB
MBB
CSB
W/
R
B
3024 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
漏1997
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3024/4
1

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