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IDT7132LA55CI Datasheet

  • IDT7132LA55CI

  • HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

  • 255.79KB

  • 16頁

  • IDT

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HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
鈼?/div>
IDT7132SA/LA
IDT7142SA/LA
Features
鈼?/div>
鈼?/div>
High-speed access
鈥?Commercial: 20/25/35/55/100ns (max.)
鈥?Industrial: 25ns (max.)
鈥?Military: 25/35/55/100ns (max.)
Low-power operation
鈥?IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
鈥?IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
On-chip port arbitration logic (IDT7132 only)
BUSY
output flag on IDT7132;
BUSY
input on IDT7142
Battery backup operation 鈥?V data retention (LA only)
TTL-compatible, single 5V 鹵10% power supply
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (鈥?0擄C to +85擄C) is available for
selected speeds
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
OL-
I/O
7L
I/O
Control
I/O
Control
I/O
OR-
I/O
7R
m
BUSY
L
(1,2)
A
10L
A
0L
Address
Decoder
11
BUSY
R
(1,2)
MEMORY
ARRAY
11
Address
Decoder
A
10R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
LOGIC
CE
R
OE
R
R/W
R
2692 drw 01
NOTES:
1. IDT7132 (MASTER):
BUSY
is open drain output and requires pullup resistor of 270鈩?
IDT7142 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor of 270鈩?
JUNE 2004
1
漏2004 Integrated Device Technology, Inc.
DSC-2692/16

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