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HIGH-SPEED 3.3V 16K x 16

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

Features:

x

x

IDT70V9269S/L

x

x

x

x

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

鈥?Commercial: 9/12/15ns (max.)

Low-power operation

鈥?IDT70V9269S

Active: 429mW (typ.)

Standby: 3.3mW (typ.)

鈥?IDT70V9269L

Active: 429mW (typ.)

Standby: 1.32mW (typ.)

Flow-through or Pipelined output mode on either port via

the

FT/PIPE

pin

Counter enable and reset features

Dual chip enables allow for depth expansion without

x

x

x

x

x

additional logic

Full synchronous operation on both ports

鈥?4ns setup to clock and 1ns hold on all Control,

data, and address inputs

鈥?Data input, address, and control registers

鈥?Fast 9ns clock to data out in the Pipelined output mode

鈥?Self-timed write allows fast cycle time

鈥?15ns cycle time, 66MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

LVTTL- compatible, single 3.3V (鹵0.3V) power supply

Industrial temperature range (鈥?0擄C to +85擄C) is available

for selected speeds

Available in a 128-pin Thin Quad Flatpack (TQFP) package

Functional Block Diagram

R/

W

L

UB

L

CE

0L

1

0

0/1

R/

W

R

UB

R

CE

0R

CE

1L

LB

L

OE

L

1

0

0/1

CE

1R

LB

R

OE

R

FT

/PIPE

L

0/1

1b 0b

b

a

1a 0a

0a 1a

a

b

0b 1b

0/1

FT

/PIPE

R

I/O

8L

-I/O

15L

I/O

Control

I/O

0L

-I/O

7L

I/O

Control

I/O

8R

-I/O

15R

I/O

0R

-I/O

7R

A

13L

A

0L

CLK

L

CNTEN

L

CNTRST

L

ADS

L

A

13R

Counter/

Address

Reg.

MEMORY

ARRAY

Counter/

Address

Reg.

A

0R

CLK

R

ADS

R

CNTEN

R

CNTRST

R

3752 drw 01

JANUARY 2001

1

漏2000 Integrated Device Technology, Inc.

DSC 3752/6

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