鈼?/div>
Counter wrap-around control
鈥?Internal mask register controls counter wrap-around
鈥?Counter-Interrupt flags to indicate wrap-around
Counter readback on address lines
Mask register readback on address lines
Global Master reset for all ports
Dual Chip Enables on all ports for easy depth expansion
Separate upper-word and lower-word controls on all ports
272-BGA package (27mm x 27mm 1.27mm ball pitch) and
256-BGA package (17mm x 17mm 1.0mm ball pitch)
Commercial and Industrial temperature ranges
JTAG boundary scan
MBIST (Memory Built-In Self Test) controller
Port - 1 Logic Block Diagram
(2)
R/
W
P1
UB
P1
CE
0P1
CE
1P1
LB
P1
OE
P1
0
1
1 /0
I/O
9P1
- I/O
17P1
I/O
0P1
- I/O
8P1
Port 1
I/O
Control
TRST
TMS
TCK
TDI
CLKMBIST
JTAG
Controller
MBIST
TDO
Addr.
Read
Back
Port 1
Readback
Register
MRST
A
0P1
- A
15P1
(1)
CNTRD
P1
MKRD
P1
MKLD
P1
CNTINC
P1
CNTLD
P1
CNTRST
P1
CLK
P1
MRST
CNTINT
P1
Port 1
Mask
Register
Priority
Decision
Logic
Port 1
Counter/
Address
Register
Port 1
Address
Decode
64KX18
Memory
Array
,
R/
W
P1
CE
0P1
CE
1P1
CLK
P1
Port 1
Interrupt
Logic
INT
P1
MRST
NOTE:
1. A
15
x is a NC for IDT70V5378.
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
5649 drw 01
AUGUST 2003
DSC-5649/3
1
漏2003 Integrated Device Technology, Inc.