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HIGH-SPEED 3.3V 16K x 36

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

x

x

IDT70V3569S

x

x

x

x

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

鈥?Commercial: 4.2/5/6ns (max.)

鈥?Industrial: 5/6ns (max)

Pipelined output mode

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

鈥?7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)

鈥?Fast 4.2ns clock to data out

鈥?1.8ns setup to clock and 0.7ns hold on all control, data, and

x

x

x

x

x

address inputs @ 133MHz

鈥?Data input, address, byte enable and control registers

鈥?Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, single 3.3V (鹵150mV) power supply for

core

LVTTL- compatible, selectable 3.3V (鹵150mV)/2.5V (鹵125mV)

power supply for I/Os and control signals on each port

Industrial temperature range (-40擄C to +85擄C) is

available for selected speeds

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-ball fine-pitch Ball Grid Array, and 256-pin Ball

Grid Array

Functional Block Diagram

BE

3L

BE

3R

BE

2L

BE

1L

BE

0L

BE

2R

BE

1R

BE

0R

R/W

L

B

W

0

L

B

W

1

L

B

W

2

L

B B

WW

3 3

L R

BB

WW

2 1

RR

B

W

0

R

R/W

R

CE

0L

CE

1L

CE

0R

CE

1R

OE

L

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

OE

R

16K x 36

MEMORY

ARRAY

I/O

0L

- I/O

35L

Din_L

Din_R

I/O

0R

- I/O

35R

CLK

L

A

13L

A

0L

CNTRST

L

ADS

L

CNTEN

L

CLK

R

,

Counter/

Address

Reg.

A

13R

ADDR_L

ADDR_R

Counter/

Address

Reg.

A

0R

CNTRST

R

ADS

R

CNTEN

R

4831 tbl 01

APRIL 2001

1

漏2001 Integrated Device Technology, Inc.

DSC 4831/8

next

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