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HIGH-SPEED 3.3V

8K x 16 DUAL-PORT

STATIC RAM

Features

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

鈥?Commercial: 15/20/25/35/55ns (max.)

鈥?Industrial: 20/25/35/55ns (max.)

Low-power operation

鈥?IDT70V25S

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

鈥?IDT70V25L

Active: 380mW (typ.)

Standby: 660

碌

W (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

IDT70V25S/L

x

x

x

x

x

x

x

x

x

x

x

x

x

IDT70V25 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = V

IH

for

BUSY

output flag on Master

M/S = V

IL

for

BUSY

input on Slave

BUSY

and Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (鹵0.3V) power supply

Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP

Industrial temperature range (-40擄C to +85擄C) is available

for selected speeds

Functional Block Diagram

R/W

L

UB

L

R/W

R

UB

R

LB

L

CE

L

OE

L

LB

R

CE

R

OE

R

,

I/O

8L

-I/O

15L

I/O

0L

-I/O

7L

BUSY

L

(1,2)

I/O

8R

-I/O

15R

I/O

Control

I/O

Control

I/O

0R

-I/O

7R

BUSY

R

(1,2)

Address

Decoder

13

A

12L

A

0L

MEMORY

ARRAY

13

Address

Decoder

A

12R

A

0R

CE

L

OE

L

R/W

L

SEM

L

INT

L

(2)

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

2.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

R

OE

R

R/W

R

SEM

R

INT

R

(2)

2944 drw 01

M/S

MAY 2000

1

DSC-2944/8

漏2000 Integrated Device Technology, Inc.

next

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