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IDT7019L15PF Datasheet

  • IDT7019L15PF

  • x9 Dual-Port SRAM

  • 17頁

  • ETC

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HIGH-SPEED
128K x 9 DUAL-PORT
STATIC RAM
Features
x
x
x
IDT7019L
x
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
鈥?Commercial: 15/20ns (max.)
Low-power operation
鈥?IDT7019L
Active: 1W (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT7019 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
x
x
x
x
x
x
x
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (鹵10%) power supply
Available in a 100-pin TQFP
Industrial temperature range (鈥?0擄C to +85擄C) is available
for selected speeds
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-8L
I/O
Control
I/O
Control
I/O
0-8R
BUSY
L
(1,2)
BUSY
R
128Kx9
MEMORY
ARRAY
7019
17
17
(1,2)
A
16L
A
0L
Address
Decoder
Address
Decoder
A
16R
A
0R
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
4840 drw 01
M/S
(1)
NOTES:
1.
BUSY
is an input as a Slave (M/S = V
IL
) and an output when it is a Master (M/S = V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JANUARY 2001
DSC-4840/2
1
漏2000 Integrated Device Technology, Inc.

IDT7019L15PF 產(chǎn)品屬性

  • IDT7019L

  • 6

  • 集成電路 (IC)

  • 存儲器

  • -

  • RAM

  • SRAM - 雙端口，異步

  • 1.125M（128K x 9）

  • 15ns

  • 并聯(lián)

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 100-LQFP

  • 100-TQFP（14x14）

  • 托盤

  • 7019L15PF

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