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IDT7017L Datasheet

  • IDT7017L

  • HIGH-SPEED 32K x 9 DUAL-PORT STATIC RAM

  • 269.27KB

  • 18頁

  • IDT

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HIGH-SPEED
32K x 9 DUAL-PORT
STATIC RAM
Features
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PRELIMINARY
IDT7017L
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True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
鈥?Commercial: 15/20ns (max.)
鈥?Industrial: 20ns (max.)
Low-power operation
鈥?IDT7017L
Active: 1W (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT7017 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
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than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (鹵10%) power supply
Available in a 100-pin TQFP
Industrial temperature range (鈥?0擄C to +85擄C) is available
for selected speeds
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-8L
I/O
Control
I/O
Control
I/O
0-8R
.
BUSY
L
A
14L
A
0L
(1,2)
BUSY
R
32Kx9
MEMORY
ARRAY
7017
15
15
(1,2)
Address
Decoder
Address
Decoder
A
14R
A
0R
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
5642 drw 01
M/S
(1)
NOTES:
1.
BUSY
is an input as a Slave (M/S = V
IL
) and an output when it is a Master (M/S = V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
NOVEMBER 2003
DSC-5642/1
1
漏2003 Integrated Device Technology, Inc.

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