音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

ID82C50A Datasheet

  • ID82C50A

  • CMOS Asynchronous Communications Element

  • 21頁

  • INTERSIL   INTERSIL

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

82C50A
March 1997
CMOS Asynchronous
Communications Element
Description
The 82C50A Asynchronous Communication Element (ACE)
is a high performance programmable Universal Asynchro-
nous Receiver/Transmitter (UART) and Baud Rate Genera-
tor (BRG) on a single chip. Using Intersil鈥檚 advanced Scaled
SAJI IV CMOS Process, the ACE will support data rates
from DC to 625K baud (0-10MHz clock).
The ACE鈥檚 receiver circuitry converts start, data, stop, and
parity bits into a parallel data word. The transmitter circuitry
converts a parallel data word into serial form and appends
the start, parity, and stop bits. The word length is program-
mable to 5, 6, 7, or 8 data bits. Stop bit selection provides a
choice of 1,1.5, or 2 stop bits.
The Baud Rate Generator divides the clock by a divisor
programmable from 1 to 2
16
-1 to provide standard RS-232C
baud rates when using any one of three industry standard
baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).
A programmable buffered clock output (BAUDOUT) provides
either a buffered oscillator or 16X (16 times the data rate)
baud rate clock for general purpose system use.
To meet the system requirements of a CPU interfacing to an
asynchronous channel, the modem control signals RTS,
CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs
have been designed with full TTL/CMOS compatibility in
order to facilitate mixed TTL/NMOS/CMOS system design.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Single Chip UART/BRG
DC to 625K Baud (DC to 10MHz Clock)
Crystal or External Clock Input
On Chip Baud Rate Generator 1 to 65535 Divisor
Generates 16X Clock
Prioritized Interrupt Mode
Fully TTL/CMOS Compatible
Microprocessor Bus Oriented Interface
80C86/80C88 Compatible
Scaled SAJI IV CMOS Process
Low Power - 1mA/MHz Typical
Modem Interface
Line Break Generation and Detection
Loopback and Echo Modes
Doubled Buffered Transmitter and Receiver
Single 5V Supply
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
TEMPERATURE
RANGE (
o
C)
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
-40 to +85
-55 to +125
625K BAUD
CP82C50A-5
IP82C50A-5
CS82C50A-5
IS82C50A-5
CD82C50A-5
ID82C50A-5
MD82C50A-5/B
PKG.
NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
Functional Diagram
CSO
CS1
CS2
ADS
A0
A1
A2
MR
DISTR
DISTR
12
13
14
25
28
27
26
35
22
21
LINE STATUS
AND CONTROL
INTERRUPT
ENABLE,
ID, & CONTROL
MICROPROCESSOR INTERFACE
24
23
30
CSOUT
DDIS
INTRPT
UART
10
RECEIVER
DIVISOR LATCH
AND BAUD RATE
GENERATOR
TRANSMITTER
MODEM
MODEM CONTROL
9
16
17
11
32
33
34
31
36
37
MODEM STATUS
38
39
SIN
RCLK
XTAL1
XTAL2
SOUT
RTS
DTR
OUT1
OUT2
CTS
DSR
DCD
RI
15 BAUDOUT
DOSTR 19
DOSTR 18
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
2958.1
1

ID82C50A相關型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！