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ICS950910YFLF-T Datasheet

  • ICS950910YFLF-T

  • Programmable Timing Control Hub for P4

  • 20頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS950910
Programmable Timing Control Hub鈩?for P4鈩?/div>
Recommended Application:
VIA P4X/P4M/KT/KN266/333 style chipsets.
Output Features:
鈥?/div>
1 - Pair of differential CPU clocks @ 3.3V (CK408)/
1 - Pair of differential open drain CPU clocks (K7)
鈥?/div>
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
鈥?/div>
3 - AGP @ 3.3V
鈥?/div>
7 - PCI @ 3.3V
鈥?/div>
1 - 48MHz @ 3.3V fixed
鈥?/div>
1 - 24_48MHz @ 3.3V
鈥?/div>
2 - REF @ 3.3V, 14.318MHz
Key Specifications:
鈥?/div>
CPU_CS - CPUT/C: <鹵250ps
鈥?/div>
CPU_CS - AGP: <鹵250ps
鈥?/div>
CPU - DDR: <鹵250ps
鈥?/div>
PCI - PCI: <500ps
鈥?/div>
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Features/Benefits:
鈥?/div>
Programmable output frequency.
鈥?/div>
Programmable output divider ratios.
鈥?/div>
Programmable output rise/fall time.
鈥?/div>
Programmable output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
DDR output buffer supports up to 200MHz.
鈥?/div>
Watchdog timer technology to reset system
if system malfunctions.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Support I
2
C Index read/write and block read/write
operations.
鈥?/div>
Uses external 14.318MHz crystal.
Frequency Table
Bit2
Bit7
FS3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit6
FS2
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
Bit5
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit4
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
105.00
140.00
210.00
174.99
80.00
106.66
160.00
133.33
100.00
133.33
200.00
166.66
100.00
133.33
200.00
166.66
AGP
MHz
70.00
70.00
70.00
70.00
53.34
53.34
53.34
53.34
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
PCI
MHz
35.00
35.00
35.00
35.00
26.66
26.66
26.66
26.66
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
Spread %
Pin Configuration
*FS0/REF0 1
GND 2
X1 3
X2 4
VDDAGP 5
*MODE/AGPCLK0 6
*SEL_408/K7/AGPCLK1 7
*(PCI_STOP#)AGPCLK2 8
GNDAGP 9
**FS1/PCICLK_F 10
***PCICLK1 11
GNDPCI 13
PCICLK3 14
PCICLK4 15
VDDPCI 16
PCICLK5 17
*(CLK_STOP#)PCICLK6 18
GND48 19
*FS3/48MHz 20
56 Vtt_PWRGD#**/REF1
55 VDDREF
54 GND
53 CPUCLKT/CPUCLKODT
52 CPUCLKC/CPUCLKODC
51 VDDCPU3.3
50 VDDCPU2.5
49 CPUC_CS
48 CPUT_CS
47 GND
46 FBOUT
ICS950910
*MULTSEL/PCICLK2 12
45 BUF_IN
44 DDRT0
43 DDRC0
42 DDRT1
41 DDRC1
40 VDD2.5
39 GND
38 DDRT2
37 DDRC2
36 DDRT3
35 DDRC3
34 VDD2.5
33 GND
32 DDRT4
31 DDRC4
30 DDRT5
29 DDRC5
MULTISEL0
Board Target
Trace/Term Z
50 ohms
50 ohms
Reference R,
Iref =
V
DD
/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Ioh = 4* I REF
Ioh = 6* I REF
Voh @ Z
*FS2/24_48MHz 21
AVDD48 22
VDD 23
GND 24
IREF 25
*(PD#)RESET# 26
SCLK 27
SDATA 28
0
1
1.0V @ 50
0.7V @ 50
56-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
*** A 120k pull-down resistor to GND is needed on this pin.
0735A鈥?3/18/04

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