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ICS950901YFLFT Datasheet

  • ICS950901YFLFT

  • Programmable Timing Control Hub for P4

  • 209.46KB

  • 20頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS950901
Programmable Timing Control Hub鈩?for P4鈩?/div>
Recommended Application:
VIA P4X266 chipset with PC133 or DDR memory.
Output Features:
鈥?/div>
2 - Pair of differential CPU clocks @ 3.3V
鈥?/div>
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
鈥?/div>
3 - AGP @ 3.3V
鈥?/div>
9 - PCI @ 3.3V
鈥?/div>
2 - IOAPIC @ 2.5V
鈥?/div>
1 - 48MHz @ 3.3V fixed
鈥?/div>
1 - 24_48MHz @ 3.3V
鈥?/div>
1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
鈥?/div>
Programmable output frequency.
鈥?/div>
Programmable output divider ratios.
鈥?/div>
Programmable output rise/fall time.
鈥?/div>
Programmable output skew.
鈥?/div>
Programmable spread percentage for EMI control.
鈥?/div>
Watchdog timer technology to reset system
if system malfunctions.
鈥?/div>
Programmable watch dog safe frequency.
鈥?/div>
Support I
2
C Index read/write and block read/write
operations.
鈥?/div>
For DDR and or PC133 SDRAM system use ICS93718
as the memory buffer.
鈥?/div>
Uses external 14.318MHz crystal.
Key Specifications:
鈥?/div>
CPU_CS - CPU0: <鹵250ps
鈥?/div>
CPU_CS - AGP: <鹵250ps
鈥?/div>
PCI - PCI: <500ps
鈥?/div>
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Pin Configuration
1
*SEL24_48/REF
VDDREF
GND
X1
X2
VDD48
**FS3/48MHz
**FS2/24_48MHz
GND
*FS0/PCICLK_F
**FS1/PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
*PD#
AGPCLK0
VDDAGP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDAPIC (2.5V)
GND
IOAPIC0
IOAPIC1
GND
VDDCPU_CS (2.5V)
CPUCLKT_CS
CPUCLKC_CS
CPUCLKT_0
CPUCLKC_0
VDDCPU (3.3V)
I REF
GND
CPUCLKT_1
CPUCLKC_1
Vtt_PWRGD#
CPU_STOP#*
PCI_STOP#*
RESET#
SDATA
SCLK
AGPCLK2
AGPCLK1
GND
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* These inputs have a internal Pull-up resistor
of 120K to VDD
** These inputs have a internal pull-down to GND
Frequency Table
FS 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C PUC LK
MHz
66.67
100.00
133.33
200.00
100.90
103.00
107.00
110.00
133.90
137.33
140.00
142.66
145.33
146.66
153.33
160.00
AGP
MHz
66.66
66.67
66.67
66.66
67.27
68.67
71.33
73.33
66.95
68.66
70.00
71.33
72.66
73.33
76.66
80.00
PC IC LK
MHz
33.33
33.33
33.33
33.33
33.63
34.33
35.67
36.67
33.48
34.33
35.00
35.67
36.33
36.67
38.33
40.00
Block Diagram
PLL2
/2
X1
X2
XTAL
XTAL
OSC
PLL1
Spread
Spectrum
Spectrum
48MHz
24_48MHz
REF
CPU
DIVDER
Stop
CPUCLKT_(1:0)
CPUCLKC_(1:0)
CPUCLKT_CS
CPUCLKC_CS
IOAPIC
IOAPIC (1:0)
CPU
DIVDER
Stop
SEL24_48
SDA
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
PCI_STOP#
CPU_STOP#
CPU_STOP#
MULTI_SEL
MULTI_SEL
Vtt_PWRGD#
Config.
Reg.
Control
Logic
IOAPIC
IOAPIC
DIVDER
PCI
DIVDER
Stop
PCICLK (7:0)
PCICLK_F
AGP
DIVDER
3
AGPCLK (2:0)
RESET#
I REF
0474F鈥?5/25/05
ICS950901

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