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ICS94222 Datasheet

  • ICS94222

  • Programmable System Frequency Generator for PII/III⑩

  • 419.86KB

  • 19頁

  • ETC

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Integrated
Circuit
Systems, Inc.
ICS94222
Advance Information
Programmable System Frequency Generator for PII/III鈩?/div>
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
鈥?/div>
3 - CPUs @2.5V, up to 166MHz.
鈥?/div>
17 - SDRAM @ 3.3V, up to 166MHz.
鈥?/div>
7 - PCI @3.3V
鈥?/div>
2 - IOAPIC @ 2.5V
鈥?/div>
1 - 48MHz, @3.3V fixed.
鈥?/div>
1 - 24MHz @ 3.3V
鈥?/div>
2 - REF @3.3V, 14.318MHz.
Features:
鈥?/div>
Programmable ouput frequency.
鈥?/div>
Programmable ouput rise/fall time.
鈥?/div>
Programmable PCI_F and PCICLK skew.
鈥?/div>
Spread spectrum for EMI control typically by 7dB to 8dB,
with programmable spread percentage.
鈥?/div>
Watchdog timer technology to reset system
if over-clocking causes malfunction.
鈥?/div>
Uses external 14.318MHz crystal.
鈥?/div>
FS pins for frequency select
Key Specifications:
鈥?/div>
CPU 鈥?CPU: <175ps
鈥?/div>
SDRAM - SDRAM: <500ps
鈥?/div>
PCI 鈥?PCI: <500ps
鈥?/div>
CPU-SDRAM: <500ps
鈥?/div>
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Pin Configuration
AVDD
*FS2/REF1
*PCI_STOP#/REF0
GND
X1
X2
VDD
*MODE/PCICLK_F
*FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD
PCICLK5
BUFFERIN
SDRAM11
SDRAM10
VDD
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDL
IOAPIC0
IOAPIC_F
GND
CPUCLK_F
CPUCLK0
VDDL
CPUCLK1
GND
CLK_STOP*
SDRAM_F
VDDSDR
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
AVDD48
24MHz/FS0*
1
48MHz/FSI*
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Functionality
Block Diagram
PLL2
梅2
ICS94222
CPU
(MHz)
80.00
75.00
83.31
66.9
103.00
112.01
68.01
100.7
120.00
114.99
109.99
105.00
140.00
150.00
124.00
133.9
48MHz
24MHz
IOAPIC_F
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X1
X2
XTAL
OSC
STOP
IOAPIC0
2
REF [1:0]
CPUCLK_F
CPUCLK (1:0)
PLL1
Spread
Spectrum
FS (3:0)
MODE
POR
LATCH
PCI
CLOCK
DIVDER
1
STOP
STOP
6
PCICLK (5:0)
PCICLK_F
CLK_STOP#
PCI_STOP#
SCLK
SDATA
BUFFERIN
Control
Logic
Config.
Reg.
STOP
16
SDRAM (15:0)
SDRAM_F
PCICLK
(MHz)
40.00
37.50
41.65
33.45
34.33
37.34
34.01
33.57
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
94222 Rev - 5/10/01
This document is confidential and should not be released
without written consents from ICS.
ADVANCE INFORMATION documents contain information on products in the
formative or design phase development. Characteristic data and other
specifications are design goals. ICS reserves the right to change or discontinue
these products without notice.

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