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ICS9248-90 Datasheet

  • ICS9248-90

  • Frequency Generator & Integrated Buffers for PENTIUM/ProTM

  • 16頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9248-90
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
General Description
The
ICS9248-90
generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.
Features include two CPU, six PCI and thirteen SDRAM
clocks. Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at 鹵0.25% modulation to reduce the EMI.
Serial programming I
2
C interface allows changing functions,
stop clock programing and Frequency selection. Additionally,
the device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up. It is not recommended to use I/O dual function pin
for the slots (ISA, PIC, CPU, DIMM). The add on card might
have a pull up or pull down.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50 鹵5% duty cycle. The REF and 24 and
48 MHz clock outputs typically provide better than 0.5V/ns
slew rates into 20pF.
Features
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3.3V outputs: SDRAM, PCI, REF, 48/24MHz
2.5V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,
center 2.6 ns.
No external load cap for C
L
=18pF crystals
鹵175 ps CPU clock skew
250ps (cycle to cycle) CPU jitter
Smooth frequency switch, with selections from 66.8
to 133 MHz CPU.
I
2
C interface for programming
3ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs (with series R)
<5ns propagation delay SDRAM from Buffer Input
Pin Configuration
Block Diagram
PLL2
/2
X1
X2
BUFFER IN
XTAL
OSC
48MHz
24MHz
IOAPIC
REF(0:1)
2
CPUCLK_F
PLL1
Spread
Spectrum
FS(0:3)
4
MODE
STOP
STOP
48-Pin SSOP
* Internal Pull-up Resistor of 240K to VDD
** Internal Pull-down resistor of 240K to GND
CPUCLK 1
Power Groups
VDDREF = REF (0:1), X1, X2
VDDPCI = PCICLK_F, PCICLK(0:4)
VDDSDR = SDRAM (0:12), supply for PLL core
VDD48 = 24MHz, 48MHz
VDDLIOAPIC = IOAPIC
VDDLCPU = CPUCLK 1, CPUCLK_F
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
LATCH
STOP
SDRAM (0:11)
12
SDRAM_F
4
POR
CPU_STOP#
PCI_STOP#
SDATA
SCLK
Control
Logic
Config.
Reg.
PCI
CLOCK
DIVDER
STOP
5
PCICLK (0:4)
PCICLKF
9248-90 Rev C 4/19/00
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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