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ICS9248-138 Datasheet

  • ICS9248-138

  • Frequency Generator & Integrated Buffers for Celeron & PII/I...

  • 12頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9248-138
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III鈩?/div>
Recommended Application:
810/810E and Solano type chipset.
Output Features:
鈥?/div>
2- CPUs @ 2.5V
鈥?/div>
9 - SDRAM @ 3.3V, including 1 free running
鈥?/div>
7 - PCICLK @ 3.3V
鈥?/div>
1 - IOAPIC @ 2.5V,
鈥?/div>
3 - 3V66MHz @ 3.3V
鈥?/div>
2 - 48MHz, @ 3.3V fixed.
鈥?/div>
1 - 24/48MHz, @3.3V selectable by I
2
C
鈥?/div>
1 - REF @v3.3V, 14.318MHz.
Features:
鈥?/div>
Up to 200MHz frequency support
鈥?/div>
Support FS0-FS4 strapping status bit for I
2
C read back.
鈥?/div>
Support power management: Through Power down
Mode from I
2
C programming.
鈥?/div>
Spread spectrum for EMI control ( 鹵 0.25% center).
鈥?/div>
Uses external 14.318MHz crystal
Skew Specifications:
鈥?/div>
CPU 鈥?CPU: <175ps
鈥?/div>
SDRAM - SDRAM: < 250ps
鈥?/div>
3V66 鈥?3V66: <175ps
鈥?/div>
PCI 鈥?PCI: <500ps
鈥?/div>
For group skew specifications, please refer to group
timing relationship.
Pin Configuration
1
*SEL24_48#/REF0
VDDREF
X1
X2
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
VDD3V66
VDDPCI
1
*FS0/PCICLK0
1
**FS1/PCICLK1
GNDPCI
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GNDPCI
PD#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
1
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
24_48MHz/FS2**
48MHz/FS3*
1
48MHz/FS4*
VDD48
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
* * These inputs have a 120K pull down to GND.
1 These are double strength.
Functionality
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
2
FS4 FS3 FS2 FS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
48MHz [1:0]
24_48MHz
REF0
CPU
DIVDER
2
CPUCLK [1:0]
SDRAM
DIVDER
8
SDRAM [7:0]
SDRAM_F
SEL24_48#
Control
SDATA
SCLK
FS[4:0]
PD#
Config.
Reg.
Logic
IOAPIC
DIVDER
IOAPIC
CPU
(MHz)
66.67
66.87
68.67
71.34
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
133.33
133.73
137.33
120.00
SDRAM
(MHz)
100.00
100.30
103.00
107.00
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
100.00
100.30
103.00
90.00
ICS9248-138
3V66
(MHz)
66.67
66.87
68.67
71.34
66.67
66.87
68.67
71.34
66.67
66.87
68.67
60.00
66.67
66.87
68.67
60.00
PCICLK
(MHz)
33.33
33.43
34.33
35.66
33.33
33.43
34.33
35.66
33.33
33.43
34.33
30.00
33.33
33.43
34.33
30.00
I OA P I C
(MHz)
16.67
16.72
17.16
17.83
16.67
16.72
17.17
17.84
16.67
16.72
17.17
15.00
16.67
16.72
17.17
15.00
PCI
DIVDER
7
PCICLK [6:0]
3V66
DIVDER
3V66 [2:0]
3
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
160.00
160.00
166.67
166.67
160.00
120.00
166.67
125.00
80.00
80.00
83.34
83.34
40.00
40.00
41.67
41.67
20.00
20.00
20.84
20.84
Additional frequencies selectable through I
2
C programming.
9248- 138 Rev A 10/03/00
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

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