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ICS9248-135 Datasheet

  • ICS9248-135

  • Frequency Generator & Integrated Buffers for Celeron & PII/I...

  • 15頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9248-135
Frequency Generator & Integrated Buffers for Celeron & PII/III鈩?amp; K6
Recommended Application:
Motherboard Single chip clock solution for SIS540,
SIS630 Pentium II/III and K6 chipsets.
Output Features:
鈥?/div>
3- CPUs @ 2.5/3.3V, up to 166MHz.
鈥?/div>
10 - SDRAM @ 3.3V, up to 166MHz
including 2 SDRAM_F's
鈥?/div>
7- PCI @3.3V,
鈥?/div>
1- 48MHz, @3.3V fixed.
鈥?/div>
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz).
鈥?/div>
2- REF @3.3V, 14.318MHz.
Features:
鈥?/div>
Up to 166MHz frequency support
鈥?/div>
Support FS0-FS3 trapping status bit for I
2
C read back.
鈥?/div>
Support power management: CPU, PCI, SDRAM stop
and Power down Mode form I
2
C programming.
鈥?/div>
Spread spectrum for EMI control (0 to -0.5%, 鹵 0.25%).
鈥?/div>
FS0, FS1, FS3 must have a internal 120K pull-Down
to GND.
鈥?/div>
Uses external 14.318MHz crystal
Skew Specifications:
鈥?/div>
CPU - CPU: < 175ps
鈥?/div>
SDRAM - SDRAM < 250ps
鈥?/div>
PCI - PCI: < 500ps
鈥?/div>
CPU - SDRAM: < 500ps
鈥?/div>
CPU (early) - PCI: 1-4ns (typ. 2ns)
Pin Configuration
VDDREF
1
* REF0/FS3
GNDREF
X1
X2
VDDPCI
*PCICLK_F/FS1
*PCICLK1/FS2
PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDD
GND
SDRAM_STOP#
**PD#
VDD
CPU_STOP#
PCI_STOP#
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1
VDDLCPU
CPUCLK_F
CPUCLK1
GNDL
CPUCLK2
VDD
SDRAM_F1
SDRAM_F0
GND
SDRAM7
SDRAM6
VDD
SDRAM5
SDRAM4
GND
SDRAM3
SDRAM2
VDD
SDRAM1
SDRAM0
VDD
1
48MHz/FS0*
24_48MHz/CPU2.5_3.3#*
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
** These inputs have a 120K pullup to VDD.
1 These are double strength.
Functionality
Block Diagram
FS3
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
ICS9248-135
CPU
(MHz)
66.6
100.0
150.0
133.3
66.8
100.0
100.0
133.3
66.8
97.0
70.0
95.0
95.0
112.0
97.0
96.2
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
REF[1:0]
CPU
DIVDER
Stop
2
CPUCLK [2:1]
CPUCLK_F
SDRAM
DIVDER
Stop
8
SDRAM [7:0]
SDRAM_F [1:0]
CPU2.5_3.3#
SDATA
SCLK
FS[3:0]
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
Config.
Reg.
Control
Logic
PCI
DIVDER
Stop
6
2
PCICLK [6:1]
PCICLK_F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SDRAM
(MHz)
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
97.0
105.0
95.0
126.7
112.0
129.3
96.2
PCICLK
(MHz)
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.2
32.1
9248-135 Rev A 1/16/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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