鈥?/div>
CPU 鈥?PCI: <500ps
Pin Configuration
VDD1
REF0/CPU_STOP#*
GND
X1
X2
VDD2
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFER IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/FS2*
GND
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
VDDL
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24/48MHz/FS1*
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Functionality
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
124.00
75.00
83.30
66.80
103.00
112.00
133.30
100.00
120.00
115.00
110.00
105.00
140.00
150.00
124.00
133.30
PCICLK
(MHz)
41.33
37.50
41.65
33.40
34.33
37.33
44.43
33.33
40.00
38.33
36.67
35.00
35.00
37.50
31.00
33.33
REF (1:0)
CPU
DIVDER
Stop
CPUCLKC0
CPUCLKT (1:0)
SEL24_48#
SDATA
SCLK
FS (3:0)
PD#
CPU_STOP#
BUFFER IN
Control
Logic
Config.
Reg.
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
SDRAM
DRIVER
SDRAM (11:0)
SDRAM_OUT
9248-114 Rev C 01/24/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-114