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ICS9148-17 Datasheet

  • ICS9148-17

  • Frequency Generator & Integrated Buffers for PENTIUM/ProTM

  • 15頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9148-17
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
General Description
The
ICS9148-17
generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors
are externally selectable with smooth frequency transitions.
Features include four CPU, six PCI, two AGP (=2xPCI) and
Twelve SDRAM clocks. Two reference outputs are available
equal to the crystal frequency. One 48 MHz for USB, and one
24 MHz clock for Super IO. Built in 鹵1.5%, 0.6% center or down
spread spectrum modulation to reduce EMI. Serial
programming I
2
C interface allows changing functions, stop
clock programing and frequency selection. Additionally, the
device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50鹵5% duty cycle. The REF and 24 and 48
MHz clock outputs typically provide better than 0.5V/ns slew
rates.
Features
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3.3V outputs: SDRAM, AGP, PCI, REF, 48/24 MHz
2.5V or 3.3V outputs: CPU
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
CPU to PCI skew = 2 to 6ns
No external load cap for C
L
=18pF crystals
250 ps max CPU, PCI clock skew
Smooth CPU frequency transition among all CPU
frequencies.
I
2
C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs.
Pin Configuration
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
STOP
48MHz
24MHz
REF (0:1)
AGP(0:1)
2
PLL1
Spread
Spectrum
FS(0:2)
MODE
CPU3.3#_2.5
STOP
4
CPUCLK (0:3)
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
CPU_STOP
3
LATCH
PCI
CLOCK
DIVDER
12
SDRAM (0:11)
5
POR
STOP
5
PCICLK (0:4)
PCICLK_F
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
Control
CPU_STOP#
PCI_STOP#
SDATA
SCLK
Logic
Config.
Reg.
PCI_STOP
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
9148-17 Rev G 4/27/00
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.

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