HiPerClockS鈩?/div>
buffer and a member of the HiPerClockS鈩?fam-
ily of High Performance Clock Solutions from
ICS. The ICS8535-21 has two single-ended clock
inputs. The single-ended clock input accepts LVCMOS or
LVTTL input levels and translate them to 3.3V LVPECL lev-
els. The clock enable is internally synchronized to eliminate
runt clock pulses on the output during asynchronous asser-
tion/deassertion of the clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics
make the ICS8535-21 ideal for those applications demand-
ing well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK0
CLK1
0
1
Q0
nQ0
Q1
nQ1
CLK_SEL
P
IN
A
SSIGNMENT
V
EE
CLK_EN
CLK_SEL
CLK0
V
EE
CLK1
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
Q0
nQ0
nc
Q1
nQ1
V
CC
ICS8535-21
14-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body package
G Package
Top View
8535AG-21
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 20, 2004