HiPerClockS鈩?/div>
member of the HiPerClockS鈩?family of High
Performance Clock Solutions from ICS. The
ICS8532-01 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the out-
puts during asynchronous assertion/deassertion of the clock
enable pin.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8532-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
B
LOCK
D
IAGRAM
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
D
Q
LE
0
1
Q0 - Q16
nQ0 - nQ16
P
IN
A
SSIGNMENT
V
CCO
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
Q0
Q1
Q2
Q3
Q4
Q5
V
CCO
nc
nc
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
CLK_EN
nc
V
CCO
1
2
3
4
5
6
7
8
9
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
V
CCO
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
nc
Vcco
ICS8532-01
33
32
31
30
29
28
10
11
12
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
nQ16
Q16
nQ15
Q15
nQ14
Q14
nQ13
Q13
nQ12
Q12
nQ11
Q11
V
CCO
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
8532AY-01
www.icst.com/products/hiperclocks.htlm
1
REV. B AUGUST 9, 2001