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devices
PCI v2.2 32-bit/33MHz Target with 3.3 VCC,
3.3/5.0 VIO
NEC 碌PD7210 compatible register layout
144 pin TQFP package
RoHS conformant (Pb-free)
Description
The i72120 GPIB-Chip is the ideal solution to implement a
IEEE488.2 GPIB interface for next generation PCI based
instruments. The GPIB-ASIC is designed to meet all of the
functional requirements for talker and listener (TL) devices
as specified by the IEEE Standards 488.1-1987 and
488.2-1987. Connected between the PCI bus and the GPIB,
this GPIB-IC provides high-level management of the GPIB to
unburden the processor and to simplify both hardware and
software design. The i72120 is fully compatible with the PCI
specification and requires only the addition of bus
driver/receiver components to implement a talker/listener
GPIB interface.
History
The IEEE Standard 488 describes a "Standard Digital Interface
for Programmable Instrumentation" which, since its
introduction in 1975 has become the most popular means of
interconnecting instruments and controllers in laboratory,
automatic test, and even industrial applications. Refined over
several years, the 488-1978 Standard, also known as The
General Purpose Interface Bus (GPIB), is a highly
sophisticated standard providing a high degree of of flexibility
to meet virtually all instrumentation requirements. The
i72120 implements all of the functions that are required to
interface to the GPIB as a talker or listener device. While it
is beyond of the scope of this document to provide a complete
explanation of the IEEE 488 Standard, a basic descriprion
follows:
The GPIB interconnects up to 15 devices over a commom
set of data control liners. Three types of devices are defined
by the standard: talker, listener, and controller, atthough
some devices may combine functions such as talker/listener
or talker/controller.
Data on the GPIB is transferred in a bit-parallel,
byte-serial fashion over eight data I/O lines
(/DIO[1]-/DIO[8]). A three-wire handshake is used to ensure
synchronisation of transmission and reception. In order to
permit more than one device to receive data at the same time,
these control lines are "open collector" so that the slowest
device controls the data rate. A number of other control lines
perform a variety of functions such as device addressing,
interrupt generation and so forth.
The i72120 implements all functional aspects of talker
and listener as defined by the 488.1-1987 Standard on a
single chip.
Pin Functions
Pinout
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
Function
NDACoen
RENo
NC
VCC
DAVi
IFCi
RENi
GND
PDN
VCC
CLK
INTAon
AD[30]
AD[28]
AD[26]
Type
OUTPUT
OUTPUT
NC
VCC
INPUT
INPUT
INPUT
GND
PDN
VCC
INPUT
OUTPUT
BIDIR
BIDIR
BIDIR
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
Function
NRFDoen
PCI_RSTNi
SRQoen
ATNi
EOIi
SRQi
NRFDi
NDACi
PDN
RSTN
VCC
AD[31]
AD[29]
AD[27]
CND
Type
OUTPUT
INPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
PDN
INPUT
VCC
BIDIR
BIDIR
BIDIR
GND
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