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FS6104-01 Datasheet

  • FS6104-01

  • Miscellaneous Clock Generator

  • 9頁

  • ETC

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August 1998
1.0
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Features
2.0
Description
Single phase-locked loop (PLL) device with a single
clock output for low-cost applications
On-board crystal oscillator with a buffered oscillator
output
5.5V to 3.3V supply
Power down input for power management
Select input for two different CLK frequencies
Minimal board footprint (8-pin 0.150" SOIC package)
Figure 1: Pin Configuration
XOUT
XIN
VSS
PWR_DWN
1
8
The FS6104 is a monolithic CMOS single PLL clock gen-
erator IC designed for cost sensitive or space limited ap-
plications.
One PLL controlled clock output is available, along with a
buffered crystal oscillator output. A low current power
down mode is available for low power requirements. The
device is packaged in an 8-pin SOIC package for a mini-
mal board footprint.
Custom factory-programmable frequencies are available;
please contact your local AMI sales representative for
more information.
SEL
VDD
CLK
REF
3.0
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Applications
FS6104
2
3
4
7
6
5
System Clock Multiplier or Divider
Replacement for High-Overtone Crystal Clock
Oscillator
8-pin (0.150鈥? SOIC
Figure 2: Block Diagram
REF
Loop
Filter
XIN
Crystal
Oscillator
R2
Counter
XOUT
Phase
Frequency
Detector
Charge
Pump
Voltage
Controlled
Oscillator
Post
Divider
Array
CLK
M
Counter
PWR_DWN
SEL
Feedback
Divider
Dual
Modulus
Prescaler
A
Counter
PLL
FS6104
American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
,62
8.13.98

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