鈩?/div>
Ethernet Controller is a
high鈥損erformance, highly integrated monolithic device, a
superset of the Fujitsu MB86965A, that incorporates a
network controller with buffer management, Manchester
encoder/decoder, 10BASE鈥揟 transceiver with on鈥揷hip
transmit and receive filters, and bus interface for a
PC/XT/AT/ISA bus. New features of the MB86965B not
present in its predecessor, the MB86965A, are summarized
below. The EtherCoupler allows implementation of adapter
solutions with as few as four chips. With its optional generic
bus mode, it is suitable for use directly on a microprocessor
bus, local bus or expansion bus.
A serial EEPROM can be interfaced to the chip for storage of
Ethernet ID and configuration settings. The EtherCoupler is
designed to be configured electronically, thus eliminating
the jumpers typically used to configure system network
adapters. When either the reset pin is activated, or a
鈥?/div>
software reset鈥?is issued by writing any value to any
on鈥揷hip address in the range x18 to x1F(hex), the
MB86965B will download three essential configuration
parameters from the EEPROM to BMPR19.
New Features of the MB86965B EtherCoupler
鈥?/div>
Full鈥揹uplex capability
鈥?/div>
External loopback mode allows testing of all 10BASE鈥揟
interface circuits
鈥?/div>
Write support for an external Flash boot PROM
鈥?/div>
Software Reset now enables the system to fully reset and
re鈥搃nitialize the controller without the need to activate the
system reset line
鈥?/div>
24 mA drive capability for IOCHRDY and IOS16 pins to
allow direct connection to the ISA bus
ADDITIONAL FEATURES
鈥?/div>
Optional, generic host interface to connect to industry鈥?/div>
standard microprocessor busses
鈥?/div>
Built鈥搃n interface for PC/XT
鈩?/div>
/AT
廬
or compatible
busses
鈥?/div>
Interface to serial EEPROM for Node ID and configura-
tion storage allows construction of jumperless, electroni-
cally鈥揷onfigurable adapters
鈥?/div>
Automatic polarity correction on twisted鈥損air
10BASE鈥揟 receive twisted鈥損air cable
鈥?/div>
Allows automatic selection of non conflicting I/O address
for self鈥搃nstalling under software control
鈥?/div>
High鈥損erformance, packet鈥揵uffer architecture pipelines
data for highest throughput
鈥?/div>
On鈥揷hip buffer management controls buffer pointers to
reduce software overhead and improve performance
鈥?/div>
Hash filter for multicast packet reception
鈥?/div>
Manchester encoder/decoder tolerates input jitter up to
鹵
18 ns
鈥?/div>
Fully compliant with ISO/ANSI/IEEE 8802鈥? specifica-
tions
鈥?/div>
Two network ports, AUI and 10BASE鈥揟, with automatic
port selection
鈥?/div>
Integrated pulse shaper, and transmit and receive filters
鈥?/div>
Selectable 150
鈩?/div>
and 100
鈩?/div>
termination for shielded or
unshielded twisted鈥損air cable, respectively
鈥?/div>
Powerdown mode to reduce power dissipation in battery鈥?/div>
powered equipment
鈥?/div>
Low鈥損ower CMOS technology
鈥?/div>
Single 5鈥搗olt power supply
鈥?/div>
160鈥損in plastic quad flat package (PQFP)
160鈥揚in
Plastic Quad
Flat Pack
(PQFP)
TOP VIEW
Figure A. Pin Configuration
鈥?鈥?/div>
next
FPT-160P-M03相關(guān)型號PDF文件下載
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EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
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EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
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