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FMS7857MTDT Datasheet

  • FMS7857MTDT

  • Ten Distributed-Output Clock Driver

  • 7頁

  • ETC

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www.fairchildsemi.com
FMS7857
Phase Locked Loop Clock Driver
Features
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Frequency Range of 60 to 170 MHz
10 outputs at 2.5 Volts
Less than 100 pS of Output to Output Skew
Less than 60 pS of Cycle to Cycle Jitter
Dedicated Power Down pin
Power Supply at 2.5V
鹵
0.2V
Commercial Temperature Range
Available in 48 pin TSSOP
operation, AVDD must be connected to 2.5 Volts. In this
mode, the PLL will compare the phase and frequency
between the incoming clock and the feedback pin. First, it
will adjust the frequency to the desired value, and then, the
phase. The PLL has wide enough bandwidth to track any
incoming clock with modulation of
鹵1%
of the clock period.
When AVDD is connected to GND, FMS7857 will be in
clock buffer mode. In this mode, the PLL is shut off and the
clock is bypassed for test proposes. Power down mode, when
connected to GND, will shut the PLL off and all the outputs
will be tri-stated.
When the input frequency falls below a suggested detection
frequency (less than 20 MHz), FMS7857 will enter the
power down mode.
FMS7857 is available in 48 pin TSSOP in commercial
temperature range.
Advanced Information
Description
FMS7857 is a zero delay clock buffer designed for high fan
out applications. It has ten outputs with one dedicated output
for feedback. All the outputs are connected to VDD at 2.5 Volts.
To reduce ground bounce noise, the Phase Locked Loop (PLL)
has a dedicated power supply pin (AVDD). For normal
Block Diagram
V
DD
Q0
Q0
Q1
Q1
PWRDWN
CONTROL
LOGIC
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
MUX
CLK
CLK
FBIN
FBIN
PLL
Q7
Q7
Q8
Q8
Q9
Q9
FBOUT
FBOUT
AV
DD
ADVANCED INFORMATION
describes products that are not in full production at the time of printing. Specifications are based on
design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
REV. 0.0.5 6/19/00

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