FDD6030L
July 1999
ADVANCE INFORMATION
FDD6030L
N-Channel Logic Level Enhancement Mode Field Effect
Transistor
General Description
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild鈥檚
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
DC/DC converters and high efficiency switching circuits
where fast switching, low in-line power loss, and
resistance to transients are needed.
Features
鈥?/div>
50 A, 30 V. R
DS(ON)
= 0.0135
鈩?/div>
@ V
GS
= 10 V
R
DS(ON)
= 0.0200
鈩?/div>
@ V
GS
= 4.5 V.
鈥?/div>
鈥?/div>
鈥?/div>
Low gate charge.
Fast switching speed.
Low Crss.
D
D
G
G
S
TO-252
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Drain-Source Voltage
Gate-Source Voltage
Maximum Drain Current
Maximum Drain Current
P
D
-Continuous
-Pulsed
o
S
T
C
=25 C unless otherwise noted
o
Parameter
Ratings
30
(Note 1)
(Note 1a)
Units
V
V
A
鹵
20
50
12
150
60
3.2
1.3
-55 to +150
Maximum Power Dissipation @ T
C
= 25 C
T
A
= 25 C
T
A
= 25 C
o
o
(Note 1)
(Note 1a)
(Note 1b)
W
T
J
, T
stg
Operating and Storage Junction Temperature Range
擄
C
Thermal Characteristics
R
胃
JC
R
胃
JA
Thermal Resistance, Junction-to- Case
Thermal Resistance, Junction-to- Ambient
(Note 1)
(Note 1a)
(Note 1b)
2.1
39
96
擄
C/W
擄
C/W
擄
C/W
Package Marking and Ordering Information
Device Marking
FDD6030L
漏1999
Fairchild Semiconductor Corporation
Device
FDD6030L
Reel Size
13鈥欌€?/div>
Tape width
16mm
Quantity
2500
FDD6030L Rev. A1
FDD6030L相關型號PDF文件下載
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型號
版本
描述
廠商
下載
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