MoBL2鈩?/div>
16-Mb (1024K x 16) Static RAM
Features
鈥?Very high speed: 55 ns and 70 ns
鈥?Wide voltage range: 1.65V to 2.2V
鈥?Ultra-low active power
鈥?Typical active current: 1.5 mA @ f = 1 MHz
鈥?Typical active current: 18 mA @ f = f
MAX
鈥?Ultra-low standby power
鈥?Easy memory expansion with CE
1
, CE
2
, and OE
features
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
鈥?Packages offered in a 48-ball FBGA
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected Chip
Enable 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW or both
BHE and BLE are HIGH. The input/output pins (I/O
0
through
I/O
15
) are placed in a high-impedance state when: deselected
Chip Enable 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW,
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH) or during a
write operation (Chip Enable 1 (CE
1
) LOW and Chip Enable 2
(CE
2
) HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then das
pins (A
0
through A
19
). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O
8
through I/O
15
) is written into the
location specified on the ad
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (<>O
7
. If Byte High Enable (BHE)
is LOW, then data from memory will appear on I/O
8
to I/O
15
.
See the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description
[1]
The CY62167DV20 is a high-performance CMOS static RAM
organized as 1024K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life
TM
(MoBL
廬
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DATA IN DRIVERS
ROW DECODER
1024K x 16
RAM ARRAY
2048 x 512 x 16
SENSE AMPS
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
BHE
WE
OE
BLE
CE
2
CE
1
Power-down
Circuit
BHE
BLE
CE
2
CE
1
Note:
1. For best practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
Cypress SemiconductorCorporation
Document #: 38-05327 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
SanJose
,
CA 95134
鈥?/div>
408-943-2600
Revised January 2, 2004
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