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CY62157DV20 Datasheet

  • CY62157DV20

  • Memory

  • 10頁

  • ETC

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CY62157DV20
MoBL2錚?/div>
8M (512K x 16) Static RAM
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Very high speed: 55 ns
Wide voltage range: 1.65V to 2.2V
Pin compatible with CY62157CV18
Ultra low active power
鈥?Typical active current: 1 mA @ f = 1 MHz
鈥?Typical active current: 10 mA @ f = fmax
Ultra low standby power
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 48-ball FBGA
deselected Chip Enable 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
)
LOW or both BHE and BLE are HIGH. The input/output pins
(I/O
0
through I/O
15
) are placed in a high-impedance state
when: deselected Chip Enable 1 (CE
1
) HIGH or Chip Enable
2 (CE
2
) LOW, outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH)
or during a write operation (Chip Enable 1 (CE
1
) LOW and
Chip Enable 2 (CE
2
) HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
), is written into the location
specified on the address pins (A
0
through A
18
). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) LOW and Chip Enable 2 (CE
2
) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O
8
to I/O
15
. See the truth table at the
back of this data sheet for a complete description of read and
write modes.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Functional Description
[1]
The CY62157DV20 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life錚?(MoBL錚? in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
512K x 16
RAM ARRAY
2048 x 256 x 16
SENSE AMPS
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
BHE
WE
OE
BLE
CE
2
CE
1
Power - down
Circuit
BHE
BLE
CE
2
CE
1
Note:
1. For best practice recommendations, please refer to the Cypress application note
System Design Guidelines
on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05136 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised March 17, 2003

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