鈥?/div>
Wide voltage range: 2.7V鈥?.6V
Ultra-low active, standby power
Easy memory expansion with CE and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Package available in a standard 44-pin TSOP Type II
(forward pinout) package
deselected (CE HIGH) or when CE is LOW and both BLE and
BHE are HIGH. The input/output pins (I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description
[1]
The CY62147V is a high-performance CMOS static RAM
organized as 256K words by 16 bits. These devices feature
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life錚?(MoBL
廬
) in
portable applications such as cellular telephones. The devices
also have an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
1
A
0
ROW DECODER
256K x 16
RAM Array
2048 x 2048
SENSE AMPS
I/O
0
鈥?I/O
7
I/O
8
鈥?I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
11
A
12
A
13
A
14
A
15
A
16
CE
Power-down
Circuit
BHE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05050 Rev. *A
鈥?/div>
3901 North First Street
A
17
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised August 28, 2002
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