鈥?/div>
Very high speed: 55 ns and 70 ns
Wide voltage range: 1.65V 鈥?2.25V
Pin-compatible with CY62147CV18
Ultra-low active power
鈥?Typical active current: 1 mA @ f = 1 MHz
鈥?Typical active current: 6 mA @ f = f
max
Ultra low standby power
Easy memory expansion with CE, and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered 48-ball BGA
mode reducing power consumption by more than 99% when
deselected (CE HIGH or both BLE and BHE are HIGH). The
input/output pins (I/O
0
through I/O
15
) are placed in a high-im-
pedance state when: deselected (CE HIGH), outputs are dis-
abled (OE HIGH), both Byte High Enable and Byte Low Enable
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Writing to the device is accomplished by asserting Chip En-
able (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
0
through
I/O
7
), is written into the location specified on the address pins
(A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table for a complete description of read and write
modes.
The CY62147DV18 is available in a 48-ball FBGA package.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Functional Description
[1]
The CY62147DV18 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life鈩?(MoBL鈩? in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K x 16
RAM Array
SENSE AMPS
I/O
0
鈥?I/O
7
I/O
8
鈥?I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
11
A
12
A
13
A
14
A
15
A
16
Pow
-
er Down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
A
17
Cypress Semiconductor Corporation
Document #: 38-05343 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 26, 2004
CY62147DV18相關(guān)型號(hào)PDF文件下載
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型號(hào)
版本
描述
廠商
下載
-
英文版
8K x 8 Static RAM
Cypress
-
英文版
128K x 8 Static RAM
CYPRESS
-
英文版
128K x 8 Static RAM
CYPRESS [C...
-
英文版
512K x 8 MoBL Static RAM
CYPRESS
-
英文版
512K x 8 MoBL Static RAM
CYPRESS [C...
-
英文版
32Kx8 Static RAM
Cypress
-
英文版
64K x 16 Static RAM
Cypress
-
英文版
64K x 16 Static RAM
Cypress
-
英文版
128K x 8 Static RAM
CYPRESS
-
英文版
128K x 8 Static RAM
CYPRESS [C...
-
英文版
1-Mbit (128K x 8) Static RAM
CYPRESS [C...
-
英文版
128K x 8 Static RAM
CYPRESS
-
英文版
128K x 8 Static RAM
CYPRESS [C...
-
英文版
128K x 16 Flash Compatible Static RAM
Cypress
-
英文版
Memory
ETC
-
英文版
128K x 16 Static RAM
Cypress
-
英文版
2-Mbit (128K x 16) Static RAM
CYPRESS
-
英文版
2-Mbit (128K x 16) Static RAM
CYPRESS [C...
-
英文版
Cypress Semiconductor [2-Mbit (256K x 8) Static RAM]
CYPRESS
-
英文版
256K x 8 Static RAM
CYPRESS
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