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CY62137BV18LL-70BAI Datasheet

  • CY62137BV18LL-70BAI

  • x16 SRAM

  • 294.77KB

  • 10頁

  • ETC

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1
CY62137BV MoBL2鈩?/div>
128K x 16 Static RAM
Features
鈥?Low voltage range:
鈥?/div>
CY62137BV18: 1.75V鈭?.95V
鈥?Ultra-low active, standby power
鈥?Easy memory expansion with CE and OE features
鈥?TTL-compatible inputs and outputs
鈥?Automatic power-down when deselected
鈥?CMOS for optimum speed/power
BHE are HIGH. The input/output pins (I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
8
to I/O
15
. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The CY62137BV18 is available in 48-ball FBGA packaging.
Functional Description
The CY62137BV18 is a high-performance CMOS static RAM
organized as 131,072 words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life鈩?(MoBL鈩? in por-
table applications such as cellular telephones. The device also
has an automatic power-down feature that significantly reduc-
es power consumption by 99% when addresses are not tog-
gling. The device can also be put into standby mode when
deselected (CE HIGH) or when CE is LOW and both BLE and
Logic Block Diagram
DATA IN DRIVERS
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
128K x 16
RAM Array
1024 X 2048
SENSE AMPS
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
BHE
BLE
Pow
-
er Down
Circuit
Cypress Semiconductor Corporation
A
10
A
11
A
12
A
13
A
14
A
15
A
16
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134
鈥?/div>
408-943-2600
March 1, 2001

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