錚?/div>
2M (128K x 16) Static RAM
Features
鈥?Very high speed: 55 ns and 70 ns
鈥?Voltage range:
鈥?CY62136CV30: 2.7V鈥?.3V
鈥?CY62136CV33: 3.0V鈥?.6V
鈥?CY62136CV: 2.7V鈥?.6V
鈥?Pin-compatible with the CY62136V
鈥?Ultra-low active power
鈥?Typical active current: 1.5 mA @ f = 1 MHz
鈥?Typical active current: 5.5 mA @ f = f
max
(70-ns
speed)
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Packages offered in a 48-ball FBGA
This is ideal for providing More Battery Life鈩?(MoBL
廬
) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O
0
through
I/O
15
) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Functional Description
[1]
The and CY62136CV are high-performance CMOS static
RAM organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
128K x 16
RAM Array
2048 x 1024
SENSE AMPS
I/O
0
鈥揑/O
7
I/O
8
鈥揑/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
12
A
13
A
11
Note:
1. For best practice recommendations, please refer to the Cypress application note 鈥淪ystem Design Guidelines鈥?on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05199 Rev. *D
鈥?/div>
3901 North First Street
A
14
A
15
A
16
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised September 20, 2002
CY62136CV33LL-70BAI相關型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
8K x 8 Static RAM
Cypress
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英文版
128K x 8 Static RAM
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英文版
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英文版
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英文版
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英文版
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英文版
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英文版
1-Mbit (128K x 8) Static RAM
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英文版
128K x 8 Static RAM
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英文版
128K x 8 Static RAM
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英文版
128K x 16 Flash Compatible Static RAM
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英文版
Memory
ETC
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英文版
128K x 16 Static RAM
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英文版
2-Mbit (128K x 16) Static RAM
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英文版
2-Mbit (128K x 16) Static RAM
CYPRESS [C...
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英文版
Cypress Semiconductor [2-Mbit (256K x 8) Static RAM]
CYPRESS
-
英文版
256K x 8 Static RAM
CYPRESS
1
2
3
4
5
6
7
8
9
10
11
12
13
