鈭?/div>
5.5V operation
鈥?CMOS for optimum speed/power
鈥?Low active power (70 ns, LL version)
鈥?330 mW (max.) (60 mA)
鈥?Low standby power (70 ns, LL version)
鈥?110
碌W
(max.) (20
碌A)
鈥?Automatic power-down when deselected
鈥?TTL-compatible inputs and outputs
鈥?Easy memory expansion with CE
1
, CE
2
, and OE options
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
1
) and write enable (WE) inputs LOW and chip enable
two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
16
).
Reading from the device is accomplished by taking chip en-
able one (CE
1
) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY62128 is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
Functional Description
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down
Logic Block Diagram
Pin Configurations
Top View
SOIC
NC
A
16
A
14
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
INPUT
BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512x 256x 8
ARRAY
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
ROW DECODER
CE
1
CE
2
WE
OE
A
4
A
5
A
6
A
7
A
12
A
14
A
16
NC
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
62128-1
TSOP I
Reverse Pinout
Top View
(not to scale)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
62128-2
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
A
10
OE
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I/ STSOP
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
62128-2
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?/div>
408-943-2600
July 1996 - Revised June 18, 1998
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