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March 2004

廬

AS7C3513B

3.3V 32K脳16 CMOS SRAM

Features

鈥?Industrial and commercial temperature

鈥?Organization: 32,768 words 脳 16 bits

鈥?Center power and ground pins

鈥?High speed

鈥?10/12/15/20 ns address access time

鈥?5, 6, 7, 8 ns output enable access time

鈥?Low power consumption: ACTIVE

鈥?288 mW / max @ 10 ns

鈥?Low power consumption: STANDBY

鈥?18 mW / max CMOS

鈥?6T 0.18m CMOS Technology

鈥?Easy memory expansion with CE, OE inputs

鈥?TTL-compatible, three-state I/O

鈥?44-pin JEDEC standard package

鈥?400 mil SOJ

鈥?400 mil TSOP 2

鈥?ESD protection > 2000 volts

鈥?Latch-up current > 200 mA

Logic block diagram

A0

A2

A3

A4

A5

A6

A7

I/O0鈥揑/O7

I/O8鈥揑/O15

Pin arrangement

V

CC

44-Pin SOJ, TSOP 2 (400 mil)

NC

A3

A2

A1

A0

CE

I/O0

I/O1

I/O2

I/O3

V

CC

GND

I/O4

I/O5

I/O6

I/O7

WE

A14

A13

A12

A11

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A4

A5

A6

OE

UB

LB

I/O15

I/O14

I/O13

I/O12

GND

V

CC

I/O11

I/O10

I/O9

I/O8

NC

A7

A8

A9

A10

NC

Row decoder

A1

32K 脳 16

Array

GND

I/O

buffer

Control circuit

Column decoder

A8

A9

A10

A12

A13

A14

A11

WE

UB

OE

LB

CE

Selection guide

-10

Maximum address access time

Maximum output enable access time

Maximum operating current

Maximum CMOS standby current

-12

12

6

75

5

AS7C3513B

-15

15

7

70

5

-20

20

8

65

5

Unit

ns

ns

mA

mA

10

5

80

5

3/24/04, v.1.2

Alliance Semiconductor

P. 1 of 10

Copyright 漏 Alliance Semiconductor. All rights reserved.

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