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AS7C3512-20JC Datasheet

  • AS7C3512-20JC

  • x8 SRAM

  • 8頁(yè)

  • ETC

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High Performance
64K脳8 3.3V
CMOS SRAM
AS7C3512
廬
Low voltage 64K脳8 CMOS SRAM
Features
鈥?Organization: 65,536 words 脳 8 bits
鈥?Single 3.3 鹵0.3V power supply
鈥?High speed
- 20/25 ns address access time
- 5/6 ns output enable access time
鈥?Very low power consumption
- Active: 216 mW max, 20 ns cycle
- Standby: 9.0 mW max, CMOS I/O
鈥?2.0V data retention
鈥?Equal access and cycle times
鈥?Easy memory expansion with CE1, CE2 and OE inputs
鈥?TTL-compatible, three-state I/O
鈥?Ideal for cache and portable computing
- 75% power reduction during CPU idle mode
鈥?32-pin JEDEC standard packages
- 300 mil PDIP and SOJ
鈥?ESD protection
鈮?/div>
2000 volts
鈥?Latch-up current
鈮?/div>
200 mA
Logic block diagram
Vcc
GND
Input buffer
Pin arrangement
DIP, SOJ
NC
NC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
A1
A2
A3
A4
A5
A6
A7
Row decoder
256脳256脳8
Array
(524,288)
Sense amp
I/O0
WE
Column decoder
Control
circuit
OE
CE1
CE2
A A A A A A A A
8 9 10 11 12 13 14 15
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
7C3512-20
20
5
60
2.5
7C3512-25
25
6
55
2.5
Unit
ns
ns
mA
mA
ALLIANCE SEMICONDUCTOR
DID 11-20015-A.
AS7C3512
I/O7

Copyright 漏1998 Alliance Semiconductor. All rights reserved.

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