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AS7C33256NTF32A-85TQC Datasheet

  • AS7C33256NTF32A-85TQC

  • 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD

  • 18頁

  • ALSC

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November 2004
廬
AS7C33256NTF32A
AS7C33256NTF36A
3.3V 256K脳32/36 Flowthrough Synchronous SRAM with NTD
TM
Features
鈥?Organization: 262,144 words 脳 32 or 36 bits
鈥?NTD
鈩?/div>
architecture for efficient bus operation
鈥?Fast clock to data access: 7.5/8.5/10 ns
鈥?Fast OE access time: 3.5/4.0 ns
鈥?Fully synchronous operation
鈥?Flow-through mode
鈥?Asynchronous output enable control
鈥?Available in 100-pin TQFP
鈥?Byte write enables
鈥?Clock enable for operation hold
鈥?Multiple chip enables for easy expansion
鈥?3.3 core power supply
鈥?2.5V or 3.3V I/O operation with separate V
DDQ
鈥?30 mW typical standby power
鈥?Self-timed write cycles
鈥?Interleaved or linear burst modes
鈥?Snooze mode for standby operation
Logic Block Diagram
A[17:0]
18
D
Address
register
Burst logic
Q
18
CLK
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D
Q
18
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
CLK
256K x 32/36
SRAM
Array
DQ[a,b,c,d]
32/36
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
OE
Output
Buffer
32/36
OE
DQ[a,b,c,d]
Selection Guide
-75
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
7.5
300
120
30
-85
10
8.5
280
110
30
-10
12
10
240
100
30
Units
ns
ns
mA
mA
mA
11/8/04, v. 1.1
Alliance Semiconductor
P. 1 of 18
Copyright 漏 Alliance Semiconductor. All rights reserved.

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