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AS7C33128PFS18A Datasheet

  • AS7C33128PFS18A

  • 3.3V 128K x 16/18 pipeline burst synchronous SRAM

  • 11頁

  • ETC

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上傳產品規(guī)格書

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January 2001
Preliminary Information
廬
AS7C33128PFS16A
AS7C33128PFS18A
3.3V 128K
脳
16/18 pipeline burst synchronous SRAM
Features
鈥?Organization: 131,072words 脳 16 or 18 bits
鈥?Fast clock speeds to 166 MHz in LVTTL/LVCMOS
鈥?Fast clock to data access: 3.5/3.8/4.0/5.0 ns
鈥?Fast OE access time: 3.5/3.8/4.0/5.0 ns
鈥?Fully synchronous register-to-register operation
鈥?鈥淔low-through鈥?mode
鈥?Single-cycle deselect
鈥?Pentium廬
*
compatible architecture and timing
鈥?Asynchronous output enable control
鈥?Economical 100-pin TQFP package
鈥?Byte write enables
鈥?Multiple chip enables for easy expansion
鈥?3.3V core power supply
鈥?2.5V or 3.3V I/O operation with separate V
DDQ
鈥?30 mW typical standby power in power down mode
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[16:0]
CLK
CS
CLR
Pin arrangement
128K 脳 16/18
Memory
array
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Burst logic
Q
A6
A7
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
17
D
CS
CLK
17
15 17
Address
register
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
16/18 16/18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
Byte Write
registers
Byte Write
registers
CLK
D
CLK
D
DQa
Q
2
OE
Enable
Q
register
Enable
Q
delay
register
CE
CLK
Output
registers
CLK
Input
registers
CLK
ZZ
Power
down
D
CLK
OE
FT
DATA [17:0]
DATA [15:0]
Selection guide
AS7C33128PFS16A AS7C33128PFS16A AS7C33128PFS16A AS7C33128PFS16A
鈥?66
鈥?50
鈥?33
鈥?00
Units
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
*
6
166
3.5
475
130
30
6.7
150
3.8
450
110
30
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14 脳 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
VSS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
Note: pins 24, 74 are NC for 脳16.
7.5
133
4
425
100
30
10
100
5
325
90
30
ns
MHz
ns
mA
mA
mA
Pentium
廬
is a registered trademark of Intel Corporation. NTD鈩?is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are
the property of their respective owners.
2/1/01; V.0.9
Alliance Semiconductor
P. 1 of 11
Copyright 漏 Alliance Semiconductor. All rights reserved.

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