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AS7C3256PFS16A Datasheet

  • AS7C3256PFS16A

  • 3.3V 256K x 16/18 pipeline burst synchronous SRAM

  • 11頁

  • ETC

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April 2000
Advance information
廬
AS7C3256PFS16A
AS7C3256PFS18A
3.3V 256K
脳
16/18 pipeline burst synchronous SRAM
鈥?Organization: 262,144 words 脳 16 or 18 bits
鈥?Fast clock speeds to 166 MHz in LVTTL/LVCMOS
鈥?Fast clock to data access: 3.5/3.8/4/5 ns
鈥?Fast OE access time: 3.5/3.5/3.8/5.0 ns
鈥?Fully synchronous register-to-register operation
鈥?鈥淔low-through鈥?mode
鈥?Single-cycle deselect
- Double-cycle deselect also available (AS7C3256PFD16A/
AS7C3256PFD18A)
鈥?Pentium廬 compatible architecture and timing
鈥?Synchronous and asynchronous output enable control
鈥?Economical 100-pin TQFP package
鈥?Byte write enables
鈥?Clock enable for operation hold
鈥?Multiple chip enables for easy expansion
鈥?3.3V core power supply
鈥?2.5V or 3.3V I/O operation with separate V
DDQ
鈥?Automatic power down: 30 mW typical standby power
鈥?NTD鈩?pipeline architecture available
(AS7C3256NTD16A/AS7C3256NTD18A)
CLR
18
D
CE
CLK
Q
Q1
18
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CLK
ADV
ADSC
ADSP
A[17:0]
CLK
CE
Burst logic
16
18
Q0
Address
register
Q
36/32
256K脳32/36
Memory
array
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
LBO
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
CCQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
GWE
BWE
BW
d
D
36/32
DQd
CLK
D
BW
c
Byte Write
registers
DQc
Q
CLK
D
BW
b
Byte Write
registers
DQb
Q
CLK
D
BW
a
Byte Write
registers
DQa
Q
4
CLK
CE0
CE1
CE2
D
Byte Write
registers
Enable
register
Q
OE
ZZ
CLK
OE
FT
36/32
DATA [35:0]
[31:0]
AS7C3256PFS16A- AS7C3256PFS16A- AS7C3256PFS16A- AS7C3256PFS16A-
3.5
3.8
4
5
Units
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
NTD鈩?is a trademark of Alliance Semiconductor Corporation
Pentium廬 is a registered trademark of Intel Corporation.
6
166.7
3.5
450
60
5
6.7
150
3.8
400
60
5
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A
A
A
A
A
A
A
Power
down
D
Enable
delay
register
Q
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CE
CLK
Output
registers
Input
registers
CLK
CLK LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14脳20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
Note: pins 24, 74 are NC for 脳16.
7.5
133.3
4
350
60
5
10
100
5
300
60
5
ns
MHz
ns
mA
mA
mA
DID 11-20027-A. 6/8/00
ALLIANCE SEMICONDUCTOR
1

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