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AS7C3128PFS36A Datasheet

  • AS7C3128PFS36A

  • 128K x 32/36 synchronous SRAM

  • 249.04KB

  • 9頁

  • ETC

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High-performance
4Mb synchronous
CMOS SRAM
AS7C3128PFS32/36A
廬
128K 脳 32/36 synchronous SRAM
Advance information
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Organization: 131,072 words 脳 32 or 36 bits
Fast clock speeds to 166 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.5/3.8/4/5 ns
Fast OE access time: 3.5/3.5/3.8/4 ns
Fully synchronous register-to-register operation
Single register 鈥榝low-through鈥?mode
Single cycle de-select
Pentium廬 compatible architecture and timing
Synchronous and asynchronous output enable control
Economical 100-pin TQFP package
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鈥?/div>
Byte write enables
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3 core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Automatic power down: 10 mW typical standby power
NTD鈩?pipeline architecture available
(AS7C3128KNTD32/36)
Logic block diagram
lbo
128k脳32/36
memory
array
clk
adv
adsc
adsp
a[16:0]
17
clk
ce
clr
d
ce address
register
clk
d
q0
burst logic
q1
17
q
Pin arrangement
A6
A7
CE0
CE1
BWd
BWc
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
15
17
gwe
bwe
bw
d
bw
c
bw
b
bw
a
ce0
ce1
ce2
q
dqd
byte write
registers
clk
d
q
dqc
byte write
registers
clk
d
q
dqb
byte write
registers
clk
d
q
dqa
byte write
registers
clk
d
ce
clk
enable
register
q
36
36
4
oe
output
registers
clk le
input
registers
clk
clk
oe
36
ft
data [35:0]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access
time
Maximum operating current
Maximum standby current
Maximum CMOS standby current
(DC)
AS7C3128PFS32/36A AS7C3128PFS32/36A AS7C3128PFS32/36A AS7C3128PFS32/36A
3.5
-3.8
-4
-5
Units
6
6.7
7.5
10
ns
166.7
150
133.3
100
MHz
3.5
350
60
5
3.8
325
60
5
4
300
60
5
5
250
60
5
ns
mA
mA
mA
6/8/00
ALLIANCE SEMICONDUCTOR
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
zz
power
down
d
enable
delay
register
q
DQPc/NC
DQc
DQc
V
DDQ
V
SSQ
DQc
DQc
DQc
DQc
V
SSQ
V
DDQ
DQc
DQc
FT
V
DD
V
DD
V
SS
DQd
DQd
V
DDQ
V
SSQ
DQd
DQd
DQd
DQd
V
SSQ
V
DDQ
DQd
DQd
DQPd/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP 14x20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
V
SS
V
DD
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
DQPa/NC
Note: Pins 1,30,51,80 are NC for 脳32
1
Copyright 漏2000 Alliance Semiconductor. All rights reserved.

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