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AS7C3128PFD36A Datasheet

  • AS7C3128PFD36A

  • 3.3V 128K x 32/36 pipeline burst synchronous SRAM

  • 10頁(yè)

  • ETC

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April 2000
Advance information
廬
AS7C3128PFD32A
AS7C3128PFD36A
3.3V 128K
脳
32/36 pipeline burst synchronous SRAM
鈥?Organization: 32,768 words 脳 16 bits
鈥?Fast clock speeds to 166 MHz in LVTTL/LVCMOS
鈥?Fast clock to data access: 3.5/3.8/4/5 ns
鈥?Fast OE access time: 3.5/3.5/3.8/5 ns
鈥?Fully synchronous operation
鈥?鈥淔low-through鈥?mode
鈥?Double-cycle deselect
- Single-cycle deselect also available (AS7C3128PFS36A/
AS7C3128PFS32A)
鈥?Pentium廬 -compatible architecture and timing
鈥?Synchronous and asynchronous output enable control
LBO
CLK
ADV
ADSC
ADSP
A[17:0]
18
CLK
CE
CLR
D
CE
CLK
GWE
BWE
BW
d
Q
Q0
鈥?Economical 100-pin TQFP package
鈥?Byte write enables
鈥?Clock enable for operation hold
鈥?Multiple chip enables for easy expansion
鈥?3.3V core power supply
鈥?2.5V or 3.3V I/O operation with separate V
DDQ
鈥?Automatic power down: 30 mW typical standby power
鈥?NTD鈩?pipeline architecture available
(AS7C3128NTD36A/ AS7C3128NTD32A)
Q1
18
16
18
Address
register
Q
36/32
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
256K脳32/36
Memory
array
DQPc/NC
DQc
DQc
V
DDQ
V
SSQ
DQc
DQc
DQc
DQc
V
SSQ
V
DDQ
DQc
DQc
FT
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SSQ
DQd
DQd
DQd
DQd
V
SSQ
V
DDQ
DQd
DQd
DQPd/NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A6
A7
CE0
CE1
BWd
BWc
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
Burst logic
D
36/32
DQd
Byte Write
registers
CLK
D
DQc
Byte Write
registers
CLK
D
DQb
Byte Write
registers
CLK
D
DQa
Byte Write
registers
CLK
D
Q
BW
c
TQFP 14x20mm
Q
BW
b
Q
4
BW
a
CE1
CE2
CE0
CE
CLK
D
Enable
register
Q
OE
Output
registers
CLK LE
Input
registers
CLK
OE
FT
36/32
DATA [35:0]
[31:0]
AS7C3128PFD36A
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
6
166.7
3.5
450
60
AS7C3128PFD36A
6.7
150
3.8
400
60
5
AS7C3128PFD36A AS7C3128PFD36A Units
7.5
133.3
4
350
60
5
10
100
5
300
60
5
ns
MHz
ns
mA
mA
mA
Maximum CMOS standby current (DC) 5
NTD鈩?is a trademark of Alliance Semiconductor Corporation.
Pentium廬 is a registered trademark of Intel Corporation.
DID 11-20011-A. 6/8/00
ALLIANCE SEMICONDUCTOR
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
A16
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ZZ
Power
down
Enable
delay
register
CLK
Q
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
DQPa/NC
Note: Pins 1,30,51,80 are NC for 脳32
1

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