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AD9396 Datasheet

  • AD9396

  • Analog/DVI Dual-Display Interface

  • 1919.13KB

  • 49頁(yè)

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Analog/DVI
Dual-Display Interface
AD9396
FEATURES
Analog/DVI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
150 MSPS maximum conversion rate
Macrovision廬 detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
DVI 1.0
150 MHz DVI receiver
Supports HDCP 1.1
R/G/B OR YPbPr
IN0
R/G/B OR YPbPr
IN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
FILT
CKINV
CKEXT
FUNCTIONAL BLOCK DIAGRAM
ANALOG INTERFACE
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
AND
CLOCK
GENERATION
R/G/B 8 脳 3
CLAMP
A/D
OR YCbCr
2 DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
REF
YCbCr MATRIX
R/G/B 8 脳 3
YCbCr (4:2:2
OR 4:4:4)
2
DATACK
HSOUT
VSOUT
SOGOUT
DE
SCL
SDA
SERIAL REGISTER
AND
POWER MANAGEMENT
MUXES
DIGITAL INTERFACE
Rx0+
Rx0鈥?/div>
Rx1+
Rx1鈥?/div>
Rx2+
Rx2鈥?/div>
RxC+
RxC鈥?/div>
RTERM
MCL
MDA
DDCSCL
DDCSDA
DVI RECEIVER
2
R/G/B 8 脳 3
OR YCbCr
DATACK
DE
HSYNC
VSYNC
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
HDCP
RGB
AD9396
Figure 1.
GENERAL DESCRIPTION
The AD9396 offers designers the flexibility of an analog
interface and digital visual interface (DVI) receiver integrated
on a single chip. Also included is support for high bandwidth
digital content protection (HDCP).
The AD9396 is a complete 8-bit, 150 MSPS monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and 720p) and FPD resolutions up
to SXGA (1280 脳 1024 @ 80 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), program-
mable gain, offset, and clamp control. The user provides only
1.8 V and 3.3 V power supply, analog input, and HSYNC.
Three-state CMOS outputs may be powered from 1.8 V to 3.3V.
The on-chip PLL generates a pixel clock from HSYNC. Pixel
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
clock output frequencies range from 12 MHz to 150 MHz. PLL
clock jitter is typically less than 700 ps p-p at 150 MHz. The
AD9396 also offers full sync processing for composite sync and
sync-on-green (SOG) applications.
The AD9396 contains a DVI-compatible receiver and supports
all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 脳 1024 @ 80 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays may now receive
encrypted video content. The AD9396 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9396 is pro-
vided in a space-saving, 100-lead, surface-mount, Pb-free plastic
LQFP and is specified over the 0潞C to 70潞C temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
漏 2005 Analog Devices, Inc. All rights reserved.
05690-001

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