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AD9380 Datasheet

  • AD9380

  • Analog/HDMI Dual-Display Interface

  • 61頁

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Analog/HDMI
Dual-Display Interface
AD9380
FEATURES
Internal key storage for HDCP
Analog/HDMI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Analog interface
8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision廬 detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping
Digital video interface
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports HDCP 1.1
Digital audio interface
HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I
2
S audio output (up to 8 channels)
FUNCTIONAL BLOCK DIAGRAM
ANALOG INTERFACE
R/G/B OR YPbPr
IN0
R/G/B OR YPbPr
IN1
HSYNC 0
HSYNC 1
HSYNC 0
HSYNC 1
SOGIN 0
SOGIN 1
COAST
FILT
CKINV
CKEXT
2:1
MUX
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
AND
CLOCK
GENERATION
R/G/B 8 脳 3
CLAMP
A/D
OR YCbCr
2 DATACK
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
REF
YCbCr MATRIX
R/G/B 8 脳 3
YCbCr (4:2:2
OR 4:4:4)
2
DATACK
HSOUT
VSOUT
SOGOUT
DE
SDA
DIGITAL INTERFACE
Rx0+
Rx0鈥?/div>
Rx1+
Rx1鈥?/div>
Rx2+
Rx2鈥?/div>
RxC+
RxC鈥?/div>
RTERM
2
R/G/B 8 脳 3
OR YCbCr
DATACK
DE
HSYNC
HDMI RECEIVER
VSYNC
RGB
4
HDCP KEYS
SCL
SERIAL REGISTER
AND
POWER MANAGEMENT
MUXES
S/PDIF
8-CHANNEL
I
2
S
SCLK
MCLK
LRCLK
Advanced TVs
HDTV
Projectors
LCD monitor
AD9380
Figure 1.
GENERAL DESCRIPTION
The AD9380 offers designers the flexibility of an analog
interface and high definition multimedia interface (HDMI)
receiver integrated on a single chip. Also included is support for
high bandwidth digital content protection (HDCP).
The AD9380 is a complete 8-bit, 150 MSPS, monolithic analog
interface optimized for capturing component video (YPbPr)
and RGB graphics signals. Its 150 MSPS encode rate capability
and full power analog bandwidth of 330 MHz supports all
HDTV formats (up to 1080p and FPD resolutions up to SXGA
(1280 脳 1024 @ 75 Hz).
The analog interface includes a 150 MHz triple ADC with
internal 1.25 V reference, a phase-locked loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only 1.8 V and 3.3 V power supplies, analog input, and HSYNC .
Three-state CMOS outputs can be powered from 1.8 V to 3.3 V.
An on-chip PLL generates a pixel clock from HSYNC.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Pixel clock output frequencies range from 12 MHz to 150 MHz.
PLL clock jitter is typically less than 700 ps p-p at 150 MHz.
The AD9380 also offers full sync processing for composite sync
and sync-on-green (SOG) applications.
The AD9380 contains an HDMI 1.1-compatible receiver and
supports all HDTV formats (up to 1080p and 720p) and display
resolutions up to SXGA (1280 脳 1024 @ 75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive
encrypted video content. The AD9380 allows for authentication
of a video receiver, decryption of encoded data at the receiver,
and renewability of the authentication during transmission, as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9380 is
provided in a space-saving, 100-lead, surface-mount, Pb-free
plastic LQFP and is specified over the 0擄C to 70擄C temperature
range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
漏 2005 Analog Devices, Inc. All rights reserved.
05688-001
APPLICATIONS
DDCSDA
DDCSCL
HDCP

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