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ACT-7000SC-200F24Q Datasheet

  • ACT-7000SC-200F24Q

  • ACT 7000SC 64-Bit Superscaler Microprocessor

  • 460.62KB

  • 25頁

  • AEROFLEX

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ACT 7000SC
64-Bit Superscaler Microprocessor
Features
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Full militarized QED RM7000 microprocessor
Dual Issue symmetric superscalar microprocessor with
instruction prefetch optimized for system level
price/performance
150, 200, 210, 225 MHz operating frequency
Consult Factory for latest speeds
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MIPS IV Superset Instruction Set Architecture
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Integrated memory management unit (ACT52xx compatible)
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Fully associative joint TLB (shared by I and D translations)
48 dual entries map 96 pages
4 entry DTLB and 4 entry ITLB
Variable page size (4KB to 16MB in 4x increments)
Specialized DSP integer Multiply-Accumulate instruction,
(MAD/MADU) and three-operand multiply instruction (MUL/U)
Per line cache locking in primaries and secondary
Bypass secondary cache option
I&D Test/Break-point (Watch) registers for emulation & debug
Performance counter for system and software tuning & debug
Ten fully prioritized vectored interrupts - 6 external, 2 internal, 2
software
Fast Hit-Writeback-Invalidate and Hit-Invalidate cache operations
for efficient cache management
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Embedded application enhancements
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High performance interface (RM52xx compatible)
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600 MB per second peak throughput
75 MHz max. freq., multiplexed address/data
Supports 1/2 clock multipliers (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)
IEEE 1149.1 JTAG (TAP) boundary scan
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Integrated primary and secondary caches - all are 4-way set
associative with 32 byte line size
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16KB instruction
16KB data: non-blocking and write-back or write-through
256KB on-chip secondary: unified, non-blocking, block writeback
Data PREFETCH instruction allows the processor to overlap cache
miss latency and instruction execution
Floating point combined multiply-add instruction increases
performance in signal processing and graphics applications
Conditional moves reduce branch frequency
Index address modes (register + register)
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High-performance floating point unit - 600 M FLOPS
maximum
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MIPS IV instruction set
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Single cycle repeat rate for common single-precision operations
and some double-precision operations
Single cycle repeat rate for single-precision combined multiply-
add operations
Two cycle repeat rate for double-precision multiply and
double-precision combined multiply-add operations
Standby reduced power mode with WAIT instruction
4 watts typical @ 2.5V Int., 3.3V I/O, 200MHz
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Fully static CMOS design with dynamic power down logic
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Embedded supply de-coupling capacitors and additional PLL
filter components
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208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), with the same pin
rotation as the commercial QED RM5261
BLOCK DIAGRAM
On - Chip 256K Byte Secondary Cache, 4 - Way Set Associative
Secondary Tags
Set A
Primary Data Cache
4 - Way Set Associative
Secondary Tags
Set B
DTag
DTLB
Secondary Tags
Set C
ITag
ITLB
Secondary Tags
Set D
Primary Instruction Cache
4 - Way Set Associative
A/D Bus
Pad Bus
Store Buffer
Write Buffer
Read Buffer
Pad Buffer
Address Buffer
Prefetch Buffer
Instruction Dispatch Unit
F Pipe Register
M Pipe Register
F-Pipe Bus
M-Pipe Bus
D Bus
Floating-Point
Load / Align
Floating-Point
Register File
Packer / Unpacker
Comparator
Floating-Point
MultAdd, Add, Sub,
Cvt, Div, Sqrt
Multiplier Array
Floating - Point Control
Joint TLB
Coprocessor 0
System / Memory
Control
PC Incrementer
Branch PC Adder
ITLB Virtuals
Program Counter
DVA
Load Aligner
Integer Register File
M Pipe
Adder
StAin/Sh
Logicals
FA Bus
IVA
F Pipe
Adder
Shifter
Logicals
DTLB Virtuals
PLL/Clocks
Int Mult. Div. Madd
eroflex Circuit Technology 鈥?MIPS RISC Microprocessors 漏 SCD7000SC REV B 7/30/01
Integer Control

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