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ACT-5271SC-150F10T Datasheet

  • ACT-5271SC-150F10T

  • Microprocessor

  • 225.24KB

  • 11頁

  • ETC

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ACT-5271SC Multichip Module
Microprocessor with 2MB Secondary Cache
Features
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Footprint Compatible with Aeroflex鈥檚 original ACT-4431SC 1MB Secondary Cache MCM in the
280 lead Ceramic Quad Flat Pack (CQFP)
QED RM5271 Dual Issue superscalar microprocessor - can issue one integer and one
floating-point instruction per cycle
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Max system clock 鈥?25MHz, Max Secondary Cache (SC) clock 75MHz, Max pipeline 150MHz
High performance system interface compatible with R4400
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Internal PLL generates selectable 2x/3x SC bus speed operation vs external system bus
speed
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Generates R4400 style system clocks
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CPU cycle rate buffering FIFO implemented in FPGA
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64-bit multiplexed system address/data bus for optimum price/performance
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High performance write protocols maximize uncached write bandwidth
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Operates at processor clock multipliers 2, 2.5 & 3
Integrated on-chip Primary Caches
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32KB instruction - 2 way set associative
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32KB data - 2 way set associative
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Pipeline restart on first double for data cache misses
Integrated in-module Secondary Cache
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2MB shared write-through
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4-128K x 36 Synchronous SRAM and 1-64K x 18 Tag RAM
Integrated memory management unit
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Fully associative joint TLB (shared by I and D translations)
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48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
High-performance floating point unit
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Single cycle repeat rate for common single precision operations and some double precision
operations
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Two cycle repeat rate for double precision multiply and double precision combined
multiply-add operations
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Single cycle repeat rate for single precision combined multiply-add operation
MIPS IV instruction set
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Floating point multiply-add instruction increases performance in signal processing and
graphics applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
Embedded application enhancements
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Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
eroflex Circuit Technology 鈥?MIPS TurboEngines For The Future 漏 SCD5271SC REV A 2/2/01

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