ACT5271
64-Bit Superscaler Microprocessor
Features
s
s
Full militarized QED RM5271 microprocessor
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
q
150,
s
High-performance floating point unit - up to 532 MFLOPS
q
Single
200, 250 MHz operating frequencies 鈥?Consult Factory for
latest speeds
q
345 Dhrystone2.1 MIPS maximum
q
SPECInt95 7.3, SPECfp95 8.3 maximum
s
cycle repeat rate for common single precision operations
and some double precision operations
q
Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
q
Single cycle repeat rate for single precision combined multiply-
add operation
s
High performance system interface compatible with RM7000,
RM5270, RM5260, RM5261, R4600, R4700 and R5000
to 125MHz memory bus operation for a 1000MBps bandwidth
from CPU to L2 cache and main memory
q
64-bitmultiplexed system address/data bus for optimum price/
performance with high performance write protocols to maximize
uncached write bandwidth
q
Supports 1/2 clock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)
q
IEEE 1149.1 JTAG boundary scan
q
Up
MIPS IV instruction set
q
Floating
point multiply-add instruction increases performance in
signal processing and graphics applications
q
Conditional moves to reduce branch frequency
q
Index address modes (register + register)
s
Embedded application enhancements
DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
q
I and D cache locking by set
q
Optional dedicated exception vector for interrupts
q
Specialized
s
Integrated on-chip caches
q
32KB/32KB
q
Virtually
instruction/data -both 2 way set associative
indexed, physically tagged
q
Write-back and write-through on per page basis
q
Pipeline restart on first double for data cache misses
s
s
Fully static CMOS design with power down logic
q
Standby
q
4.2
reduced power mode with WAIT instruction
Watts typical power @ 200MHz
q
2.5V core with 3.3V IO鈥檚
s
s
Integrated secondary cache controller (R5000 compatible)
q
Supports 512K or 2MByte block write-through secondary
208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
179-pin PGA package (Future
Product)
(P10)
s
Integrated memory management unit
q
Fully
q
48
associative joint TLB (shared by I and D translations)
dual entries map 96 pages
q
Variable page size (4KB to 16MB in 4x increments)
s
BLOCK DIAGRAM
Preliminary
eroflex Circuit Technology 鈥?RISC TurboEngines For The Future 漏 SCD5271 REV 1 12/22/98
1
2
3
4
5
