ACT 5261
64-Bit Superscaler Microprocessor
Features
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Full militarized QED RM5261 microprocessor
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
150, 200, 250 MHz operating frequencies 鈥?Consult Factory
for latest speeds
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345 Dhrystone 2.1 MIPS
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SPECInt95 7.3, SPECfp95 8.3
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133,
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High-performance floating point unit: up to 500 MFLOPS
cycle repeat rate for common single precision operations
and some double precision operations
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Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
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Single cycle repeat rate for single precision combined multiply-
add operation
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Single
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Pinout compatible with popular RM5260
High performance system interface compatible with RM5260,
RM 5270, RM5271, RM7000, R4600, R4700 and R5000
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64-bit
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鈥?MIPS IV instruction set
point multiply-add instruction increases performance in
signal processing and graphics applications
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Conditional moves to reduce branch frequency
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Index address modes (register + register)
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Floating
multiplexed system address/data bus for optimum price/
performance
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High performance write protocols maximize uncached write
bandwidth
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Supports 1/2 clock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)
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IEEE 1149.1 JTAG boundary scan
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Embedded application enhancements
DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
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I and D cache locking by set
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Optional dedicated exception vector for interrupts
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Specialized
鈥?Integrated on-chip caches
instruction - 2 way set associative
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32KB data - 2 way set associative
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Virtually indexed, physically tagged
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Write-back and write-through on per page basis
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Pipeline restart on first double for data cache misses
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32KB
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Fully static CMOS design with power down logic
reduced power mode with WAIT instruction
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3.6 Watts typical power @ 200MHz
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2.5V core with 3.3V IO鈥檚
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Standby
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208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint
179-pin PGA package (Future
Product)
(P10)
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鈥?Integrated memory management unit
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Fully
associative joint TLB (shared by I and D translations)
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48 dual entries map 96 pages
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Variable page size (4KB to 16MB in 4x increments)
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Block Diagram
Preliminary
eroflex Circuit Technology 鈥?RISC TurboEngines For The Future 漏 SCD5261 REV 1 12/22/98
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