鈼?/div>
Flexible Architecture with Numerous Configuration Options
鈥?Port arbitration schemes utilizing round robin algorithms
鈥?Virtual channels arbitration based on priority
鈥?Automatic per port link width negotiation to x8, x4, x2 or x1
鈥?Automatic lane reversal on all ports
鈥?Automatic polarity inversion on all lanes
鈥?Supports locked transactions, allowing use with legacy soft-
ware
鈥?Ability to load device configuration from serial EEPROM
鈥?Ability to control device via SMBus
Highly Integrated Solution
鈥?Requires no external components
鈥?Incorporates on-chip internal memory for packet buffering and
queueing
鈥?Integrates sixty-four 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
鈥?Redundant upstream port failover capability
鈥?Supports optional PCI Express end-to-end CRC checking
Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
SerDes
DL/Transaction Layer
Route Table
Port
Arbitration
16-Port Switch Core
Frame Buffer
Scheduler
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
SerDes
SerDes
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
64 PCI Express Lanes
Up to 8 x8 ports or 16 x4 Ports
Figure 1 Internal Block Diagram
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2007 Integrated Device Technology, Inc.
July 19, 2007