鈼?/div>
High Performance PCI Express Switch
鈥?Sixteen 2.5 Gbps PCI Express lanes
鈥?Seven switch ports
鈥?Upstream port configurable up to x8
鈥?Two downstream ports configurable up to x4, four downstream
ports are x1
鈥?Low-latency cut-through switch architecture
鈥?Support for Max Payload Sizes up to 2048 bytes
鈥?One virtual channel
鈥?Eight traffic classes
鈥?PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
鈥?Automatic per port link width negotiation to x8, x4, x2 or x1
鈥?Automatic lane reversal on all ports
鈥?Automatic polarity inversion on all lanes
鈥?Ability to load device configuration from serial EEPROM
鈼?/div>
Legacy Support
鈥?PCI compatible INTx emulation
鈥?Bus locking
Highly Integrated Solution
鈥?Requires no external components
鈥?Incorporates on-chip internal memory for packet buffering and
queueing
鈥?Integrates sixteen 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
鈥?Supports ECRC and Advanced Error Reporting
鈥?Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
鈥?Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
鈥?Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
Power Management
鈥?Utilizes advanced low-power design techniques to achieve low
typical power consumption
鈥?Supports PCI Power Management Interface specification (PCI-
PM 1.1)
鈥?Supports device power management states: D0, D3
hot
and
D3
cold
鈥?Unused SerDes are disabled
Block Diagram
7-Port Switch Core / 16 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
TL
DLL
Mux/Demux
Phy
Logical
Layer
TL
DLL
Mux/Demux
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes SerDes
SerDes
SerDes
SerDes SerDes
SerDes
SerDes
SerDes SerDes
SerDes
SerDes
(Port 0)
(Port 1)
(Port 2)
(Port 3)
(Port 6)
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2007 Integrated Device Technology, Inc.
February 8, 2007
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