24-Lane 3-Port
PCI Express廬 Switch
89HPES24N3A
Product Brief
Device Overview
The 89HPES24N3A is a member of the IDT PRECISE鈩?family of
PCI Express廬 switching solutions offering the next-generation I/O inter-
connect standard. The PES24N3A is a 24-lane, 3-port peripheral chip
that performs PCI Express Packet switching with a feature set optimized
for high performance applications such as servers, storage, and commu-
nications/networking. It provides high-performance I/O connectivity and
switching functions between a PCI Express upstream port and two
downstream ports or peer-to-peer switching between downstream ports.
The 89HPES24N3A offers an enhanced architecture and feature set
in a package that is pin-compatible with the first generation
89HPES24N3 24-lane, 3-port PCIe switch.
Features
鈼?/div>
High Performance PCI Express Switch
鈥?Twenty-four 2.5 Gbps PCI Express lanes
鈥?Three switch ports
鈥?Upstream port configurable up to x8
鈥?Downstream ports configurable up to x8
鈥?Low-latency cut-through switch architecture
鈥?Support for Max Payload Size up to 2048 bytes
鈥?One virtual channel
鈥?Eight traffic classes
鈥?PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
鈥?Automatic per port link width negotiation to x8, x4, x2 or x1
鈥?Automatic lane reversal on all ports
鈥?Automatic polarity inversion on all lanes
鈥?Ability to load device configuration from serial EEPROM
鈼?/div>
Legacy Support
鈥?PCI compatible INTx emulation
鈥?Bus locking
鈼?/div>
Highly Integrated Solution
鈥?Requires no external components
鈥?Incorporates on-chip internal memory for packet buffering and
queueing
鈥?Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/
10B encoder/decoder (no separate transceivers needed)
鈼?/div>
Reliability, Availability, and Serviceability (RAS) Features
鈥?Supports ECRC and Advanced Error Reporting
鈥?Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
鈥?Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
鈥?Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
鈼?/div>
Block Diagram
3-Port Switch Core
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
...
...
...
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
SerDes
24 PCI Express Lanes
x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 2
漏
2007 Integrated Device Technology, Inc.
February 8, 2007
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