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89HPES12T3G2ZABCG Datasheet

  • 89HPES12T3G2ZABCG

  • 12-Lane 3-Port Gen2 PCI Express Switch

  • 563.23KB

  • 31頁

  • IDT

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12-Lane 3-Port
Gen2 PCI Express廬 Switch
廬
89HPES12T3G2
Data Sheet
Advance Information*
Device Overview
The 89HPES12T3G2 is a member of IDT鈥檚 PRECISE鈩?family of PCI
Express廬 switching solutions. The PES12T3G2 is a 12-lane, 3-port
Gen2 peripheral chip that performs PCI Express Base switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
High Performance PCI Express Switch
鈥?Twelve 5 Gbps Gen2 PCI Express lanes
鈥?Three switch ports
鈥?One x4 upstream port
鈥?Two x4 downstream ports
鈥?Low latency cut-through switch architecture
鈥?Support for Max Payload Size up to 2048 bytes
鈥?One virtual channel
鈥?Eight traffic classes
鈥?PCI Express Base Specification Revision 2.0 compliant
鈼?/div>
Flexible Architecture with Numerous Configuration Options
鈥?Automatic per port link width negotiation to x4, x2 or x1
鈥?Automatic lane reversal on all ports
鈥?Automatic polarity inversion
鈥?Ability to load device configuration from serial EEPROM
鈼?/div>
Features
Block Diagram
3-Port Switch Core / 12 PCI Express Lanes
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Multiplexer / Demultiplexer
Phy
Logical
Layer
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
Figure 1 Internal Block Diagram
(Port 4)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 31
漏
2007 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
September 4, 2007
DSC 6930
Advance Information
Legacy Support
鈥?PCI compatible INTx emulation
鈥?Bus locking
鈼?/div>
Highly Integrated Solution
鈥?Incorporates on-chip internal memory for packet buffering and
queueing
鈥?Integrates twelve 5 Gbps embedded SerDes with 8b/10b
encoder/decoder (no separate transceivers needed)
鈥?Receive equalization (RxEQ)
鈼?/div>
Reliability, Availability, and Serviceability (RAS) Features
鈥?Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
鈥?Supports ECRC and Advanced Error Reporting
鈥?Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
鈥?Compatible with Hot-Plug I/O expanders used on PC mother-
boards
鈥?Supports Hot-Swap
鈼?/div>
Power Management
鈥?Utilizes advanced low-power design techniques to achieve low
typical power consumption
鈥?Support PCI Express Power Management Interface specifica-
tion (PCI-PM 2.0)
鈼?/div>

89HPES12T3G2ZABCG 產(chǎn)品屬性

  • 0現(xiàn)貨

  • 停產(chǎn)

  • PRECISE?

  • 托盤

  • 停產(chǎn)

  • 開關(guān)接口

  • PCI Express

  • 3.3V

  • 324-BGA

  • 324-CABGA（19x19）

  • 表面貼裝型

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