12 Lane 3-Port
PCI Express廬 Switch
89HPES12N3A
Product Brief
Device Overview
The 89HPES12N3A, a 12 lane 3-port PCI Express廬 switch, is a
member of the IDT PRECISE鈩?family of PCI Express switching solu-
tions. The PES12N3A is a peripheral chip that performs PCI Express
Packet switching with a feature set optimized for high performance
applications such as servers and storage. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports or peer-to-peer switching between downstream ports.
The 89HPES12N3A offers an enhanced architecture and feature set
in a package that is pin-compatible with the first generation
89HPES12N3 12-lane, 3-port PCIe switch.
Features
鈼?/div>
High Performance PCI Express Switch
鈥?Twelve 2.5Gbps PCI Express lanes
鈥?Three switch ports
鈥?Upstream port configurable up to x4
鈥?Downstream ports configurable up to x4
鈥?Low-latency cut-through switch architecture
鈥?Support for Max Payload Sizes up to 2048 bytes
鈥?One virtual channel
鈥?Eight traffic classes
鈥?PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
鈥?Automatic per port link width negotiation to x4, x2 or x1
鈥?Automatic lane reversal on all ports
鈥?Automatic polarity inversion on all lanes
鈥?Ability to load device configuration from serial EEPROM
鈼?/div>
Legacy Support
鈥?PCI compatible INTx emulation
鈥?Bus locking
鈼?/div>
Highly Integrated Solution
鈥?Requires no external components
鈥?Incorporates on-chip internal memory for packet buffering and
queueing
鈥?Integrates twelve 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
鈼?/div>
Reliability, Availability, and Serviceability (RAS) Features
鈥?Supports ECRC and Advanced Error Reporting
鈥?Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
鈥?Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
鈥?Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
鈼?/div>
Block Diagram
3-Port Switch Core
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Scheduler
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes SerDes SerDes SerDes
SerDes
SerDes SerDes
SerDes
SerDes SerDes SerDes SerDes
12 PCI Express Lanes
One x4 Upstream Port and Two x4 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 2
漏
2007 Integrated Device Technology, Inc.
February 8, 2007
89HPES12N3YCBCG 產(chǎn)品屬性
0現(xiàn)貨
停產(chǎn)
PRECISE?
托盤
停產(chǎn)
開關(guān)接口
PCI Express
3.3V
324-BGA
324-CABGA（19x19）
表面貼裝型
89HPES12N3YCBCG相關(guān)型號(hào)PDF文件下載
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